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october 2004 1/86 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. rev. 1 stpc? vega x86 core pc compatible soc with ethernet and usb preliminary data pentium ? ii class processor core 64-bit sdram controller running at up to 100 mhz pci 2.1 compliant master/slave controller isa master / slave dual port usb host controller (ohci) 10/100 ethernet mac 1) integrated peripheral controller with suppport for external rtc ultra dma-66 ide controller power management unit 16-bit local bus interface i2c bus controller uart (1 rxtx) ieee 1149.1 jtag interface 8 general purpose io programmable clocks 0.18 micron technology 1.8 v core & 3.3 v i/os low power consumption device description the stpc vega integrates a fully static pentium ? ii ? class processor, fully compatible with industry standards, and combines it with a powerful chipset to provide a general purpose pc compati- ble subsystem on a single device. the device is packaged in a 388 ball grid array (pbga). 1- the usage of the internal mac 10/100 is very restricted. for more information see 10/100 ethernet controller description. 1 pbga388 s t p c v e g a p-ii? class core host i/f sdram i/f pci i/f pci uide isa i/f pci i/f isa bus lb i/f local bus ipc jtag pmu gpio usb 10/100 mac i 2 c isa bus block diagram
table of contents 86 2/86 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 feature multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6 clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1 basic clocks and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.2 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.3 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.4 isa interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.5 x-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.6 local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.7 ide interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.8 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.9 media access controller (mac) ethernet interface (lan) . . . . . . 21 2.2.10 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.11 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 2.2.12 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 signal detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 strap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1 power on strap register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.1 adpc strap register 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2 adpc strap register 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.3 adpc strap register 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.1 power/ground connections/decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.2 unused input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.3 reserved designated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5.1 power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5.2 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5.3 sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.5.4 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.5.5 ipc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5.6 isa interface ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5.7 local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5.8 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 4.5.9 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1
table of contents 3/86 4.5.10 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1 388-pin package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2 388-pin package thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3 soldering recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6 design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1.1 file server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1.2 graphics terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.2 stpc configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.2.1 local bus / isa bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.2.2 clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3 architecture recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.1 power decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.2 14mhz oscillator stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.3 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.4 pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.5 local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.6 ipc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.7 ide / isa dynamic demultiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.8 basic audio using ide interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.9 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 6.3.10 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 6.4 place and route recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.1 general recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.2 pll definition and implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.3 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.4 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.5 thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6 debug methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.6.1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.6.2 boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.6.3 isa mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.6.4 local bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.6.5 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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stpc? vega 4/86 x86 processor x86 pentium? ii class processor running in x2 mode -3 issue integer six-stage pipeline/clock -3 issue mmx?/clock -pipelined fpu bus clock with skew correction internal core clocks generated as multiples of bus clock with multiplic ation factors of x2, x2.5, x3, x3.5 sdram interface 64-bit data bus 100 mhz maximum sdram clock 8 mbyte to 256 mbyte memory size (only the upper 128mbyte cacheable) supports 16 mbit to 256 mbit memories support for -8 to -15 memory parts supports buffered and non-buffered dimms supports registered dimms programmable latency pci controller master/slave compatible with pci vers ion 2.1 specification integrated pci arbitration interface. up to three external masters can be directly connected master/slave bridge to usb, lan, uide & isa cycles support for burst read/write from pci master 0.20x, 0.25x, 0.33x and 0.5x host clock pci clock. automatically selected. isa master/slave generates the isa clock from either 14.318 mhz oscillator clock or pci clock supports programmable extra wait state for isa cycles supports i/o recovery time for back to back i/o cycles fast gate a20 and fast reset supports flash rom supports isa hidden refresh buffered dma and isa master cycles to reduce the bandwidth utilization of pci and system bus local bus multiplexed with isa interface 16-bit bus data path with word steering capability two cacheable banks of 32 mbyte flash devices (boot block shadowed from 000c0000h to 000fffffh) programmable timing with host clock granularity for flash accesses 32-bit flash burst support two-level hardware key protection for flash boot block protection up to eight io devices (four chipselects) supported with programmable start address & size io device timing (setup & recovery time) programmable integrated peripherals controller interrupt controller: 8259 compatible (two interrupt controllers) dma controller: 8237 co mpatible (two dma controllers) page register counter 0 and counter 1 gates are always on, counter 2 is controlled by writing to port b supports external rtc ultra dma-66 ide controller supports ide hard drives larger than 528 mbytes support for two connectors to allow up to four drives support for cd-rom and tape peripherals support for 11.1/16.6 mbytes/second, i/o channel ready pio data transfers supports up to 66 mbytes/second, udma data transfers ultra dma supports crc-16 error checking protocol (no correction supported) pio: 0 to 5, dma: 0 to 2, udma: 0 to 4 backward compatibility with ide (ata-1) 8 gpio individual pins programmable as either input or output interrupt generation with selectable masking 1
stpc? vega 5/86 10/100 ethernet controller the usage of vega internal mac is very restricted and tested only under linux operating system with the specific configuration 100mb/s half and full duplex . any other functional configuration is not guaranteed by stmicroelectronics. problem that maybe occur is a file transfer corruption , however the use of the internal mac for browsing applications or http session does not causes problem. compliant with ieee 802.3, 802.3u specification supports 10/100 mb/s data transfer rates ieee 802.3 compliant mii interface to talk to an external physical layer (phy) vlan support supports both full-duplex and half-duplex operations supports csma/cd protocol for half-duplex supports flow-control for full-duplex operation collision detection and auto retransmission on collisions in half-duplex mode management support using a variety of counters preamble generation and removal automatic 32-bit crc generation and checking optional insertion of pad/crc32 on transmit options for automatic pad stripping on the receive packets provides external and internal loop back capability on the mii interface contains a variety of flexible address filtering modes on the ethernet side: - one 48-bit perfect address - 64 hash-filtered multicast addresses - pass all multicast addresses - promiscuous mode - pass all incoming packets with a status report usb host controller open hci rev 1.1 compatible usb rev 1.1 compatible root hub with two down-stream ports with power switching control support of both low & high speed usb devices support of system management interupt (smi) uart one uart rxtx only programmable word length, stop bits and parity programmable baud rate generator interrupt generator loop-back mode scratch register two 16-byte fifos power management unit four power saving modes: on, doze, standby, suspend programmable system activity detector supports stpclk# i2c bus controller one i2c compliant master/slave bus controller slow and fast modes supported jtag function boundary scan chain function 1
stpc? vega 6/86 1 introduction at the heart of the stpc vega is an advanced processor block that includes a powerful pentium ? ii class processor core along with a 64-bit sdram controller, a high speed pci local- bus controller and industry standard pc chip set functions (interrupt cont roller, u-dma controller, interval timer and isa bus) and u-ide controller. the processor bus runs at the speed of half the processor speed (x2 mode) or x3 or x3.5 modes. the stmicroelectronics pentium? ii class processor core is embedded with standard and application specific peripheral modules on the same silicon die. the core has all the functionality of the intel tm standard pentium? ii class processor products, including the low power system management mode (smm). system management mode (smm) provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. while running in isolated smm address space, the smm interrupt routine can execute without interfering with the operating system or application programs. the ?standard? pc chipset functions (dma, interrupt controller, timers, power management logic) are integrated with the pentium? ii class processor core. the pci bus is the main data communication link to the stpc vega chip. the stpc vega translates appropriate host bus i/o and memory cycles onto the pci bus. it also supports generation of configuration cycles on the pci bus. the stpc vega, as a pci bus agent (host bridge class), fully complies wit h pci specification 2.1. the chip-set also implements the pci mandatory header registers in type 0 pci configuration space for easy porting of pci aware system bios. the device contains a pci arbitration function for three external pci devices. the stpc vega integrates an isa bus controller. peripheral modules such as parallel and serial communications ports, keyboard controllers and additional isa devices can be accessed by the stpc vega chip set through this bus. an industry standard u-ide (ata 2) controller is built in to the stpc vega and connected internally via the pci bus. the general purpose input/output (gpio) interface provides an 8-bi t i/o facility, using 8 dedicated device pins. it is organised using one 8- bit register. each gpio port can be configured as an input or an output simply by programming the associated port direction control register. all gpio ports are configured as inputs at reset, which also latches the input levels into the strap registers. the input states of the ports are thus recorded automatically at reset, and this can be used as a strap register anywhere in the system. 1.1 memory controller the stpc vega handles the memory data (data) bus directly, controlling up to 256 mbytes. the sdram controller supports accesses to the memory banks to/from the cpu (via the host). parity is not supported. the sdram controller only supports 64 bit wide memory banks. four memory banks (if dimms are used; single sided or two double-sided dimms) are supported in the following conf igurations (see table 1-1. ) table 1-1. memory configurations the sdram controller supports buffered or unbuffered sdram but not edo or fpm modes. sdrams must support full page mode type access. the stpc memory contro ller provides various programmable sdram parameters to allow the sdram interface to be optimized for different processor bus speeds, sdram speed grades and cas latency. memory bank size number organisation device size 1mx64 4 1mx16 16mbits 2mx64 8 2mx8 4mx64 16 4mx4 4mx64 4 2mx16x2 64mbits 8mx64 8 4mx8x2 16mx64 16 8mx4x2 2mx64 2 500kx32x4 4mx64 4 1mx16x4 8mx64 8 2mx8x4 16mx64 16 4mx4x4 4mx64 2 1mx32x4 128mbits 8mx64 4 2mx16x4 16mx64 8 4mx8x4 32mx64 16 8mx4x4 8mx64 2 2mx32x4 256mbits 16mx64 4 2mx16x4 32mx64 8 2mx8x4 1
stpc? vega 7/86 1.2 feature multiplexing the stpc vega bga package has 388 balls. this however is not sufficient for all of the integrated functions available; some features therefore share the same balls and cannot thus be used at the same time. the stpc vega configuration is done by ?strap options?. this is a set of pull-up or pull- down resistors (see section 3 for more details), checked on reset, which auto-configure the stpc vega. there are 2 multiplexed functions, these are the external isa bus and the local bus interfaces. 1.3 power management the stpc vega core is compliant with the advanced power management (apm) specification to provide a standard method by which the bios can control the power used by personal computers. the power management unit (pmu) module controls the power consumption, providing a comprehensive set of features that controls the power usage and supports compliance with the united states environmental protection agency's energy star computer program. the pmu pr ovides the following hardware structures to assist the software in managing the system power consumption: ? system activity detection ? 3 power-down timers detecting system inactivity: - doze timer (short durations) - stand-by timer (medium durations) - suspend timer (long durations) ? house-keeping ac tivity detection ? house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand- by state ? peripheral activity detection ? peripheral timer detecting peripheral inactivity ? susp# modulation to adjust the system per- formance in various power down states of the system including fu ll power-on state ? power control outputs to disable power from dif- ferent planes of the board lack of system activity for progressively longer periods of time is detected by the three power down timers. these timers can generate smi interrupts to cpu so th at the smm software can put the system in decreasing states of power consumption. alternatively, system activity in a power down state can generate an smi interrupt to allow the software to bring the system back up to full power-on state. the chip-set supports up to three power down states described above; these correspond to decreasing levels of power savings. power down puts the stpc vega into suspend mode. the processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. during suspend mode, internal clocks are stopped. removing power-down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. because of the static nature of the core, no internal data is lost. 1.4 jtag jtag stands for joint test action group and is the popular name for ieee std. 1149.1, standard test access port and boundary-scan architecture. this built-in circuitry is used to assist in the test, maintenance and support of functional circuit blocks through boundary scan chain. 1.5 i 2 c the i 2 c (inter-integrated circuit) controller built into the stpc vega provides a two-wire communi- cation link between the stpc and external inte- grated circuits. master and slave modes are avail- able in slow and fast modes. 1
stpc? vega 8/86 figure 1-1. functional description 1.6 clock tree the stpc vega integrates many features and generates all its clocks from a single 14mhz oscillator. this results in multiple clock domains as described in figure 1-2 . the speed of the plls is either fixed (devclk), either programmable by strap option (hclk) either programmable by software (gpclk, mclk). when in synchronized mode, mclk speed is fixed to hclko speed and hclki is generated from mclki. local bus interface x86 core host i/f sdram controller host to pci pci bus isa ipc isa bus u-ide pmu gpios usb external stpc envelope devices 10/100 mac jtag i 2 c uart 1
stpc? vega 9/86 figure 1-2. stpc vega clock architecture ipc sdram controller north bridge 14.31818 mhz xtalo xtali osc14m isaclk 1/4 (14mhz) 1/2 hclk pll pciclki pciclko south bridge 1/2 1/3 hclk mclk pll mclki mclko cpu x2 local bus host isa hclki hclko devclk periclk (24 mhz) pll uart usb 48mhz 1/4 1/26 1/6 1/2 1
stpc? vega 10/86 figure 1-3. typical isa-based application. stpc vega isa pci 4x 16-bit sdrams super i/o 2x eide flash keyboard / mouse serial ports parallel port floppy irq dma.req dma.ack dmux dmux mux mux rtc gpios gpclk 1
stpc? vega 11/86 2 pin description 2.1 introduction the stpc vega integrates most of the functionalities of the pc architecture. as a result, many of the traditional interconnections between the host pc microprocessor and the peripheral devices are totally internal to the stpc vega. this offers improved performance due to the tight coupling of the processor core and these peripherals. as a result many of the external pin connections are made directly to the on-chip peripheral functions. table 2-1 describes the physical implementation listing signal type and functionality. table 2-2 provides a full pin listing and pin descriptions. table 2-6 provides a full listing of the stpc vega package physical pin connections. note: several interface pins are multiplexed with other functions. refer to table 2-4 and table 2-5 for further details. table 2-1. signal description group name qty basic clocks, reset & xtal 8 memory interface 93 pci interface 57 isa 65 86 uide 10 local bus 50 analog (pll) gnd 4 analog (pll) v dd 5 gpio 8 ethernet mac (media access controller) 17 usb 6 uart 2 i 2 c2 jtag 4 v dd 1.8 v 4 v dd 3.3 v 12 gnd 68 unconnected 9 misc 3 total pin count 388 1
stpc? vega 12/86 table 2-2. defini tion of signal pins signal name dir buffer type 2 description qty basic clocks and resets sysrseti# i schmitt_ft system power good input 1 sysrsto# o bt8trp_tc system reset output 1 xtali i osci13b 14.318 mhz crystal input external oscillator input 1 xtalo i/o 14.318 mhz crystal output 1 hclk i/o bd4strp_ft host clock (test) 1 dev_clk o bt8trp_tc peripheral clock 1 power supplies vdd 3.3v power supply for i/o pads 12 vdd_core 1.8v core power supply 4 vdd33_cpuclk_pll 3.3v power supply for cpu pll clock 1 vdd18_cpuclk_pll 1.8v power supply for cpu pll clock 1 v dd _xxx_pll 3.3v power supply for pll clocks 3 vss_xxx_pll ground plane for pll clocks 4 gnd digital ground plane 68 memory interface mclki i tlcht_tc memory clock input 1 mclko o bt8trp_tc memory clock output 1 cs#[1:0] o db8strp_tc bank chip select 2 ma[10:0] o bd16staruqp_tc memory row & column address 1 ma[11]/cs#[2] o bd16staruqp_tc bank chip select / memory address 1 ma[12] o bd16staruqp_tc memory row & column address 1 ba[0] o bd16staruqp_tc bank address 1 ba[1]/cs#[3] o bd16staruqp_tc bank address / bank chip select 1 ras#[1:0] o bd16staruqp_tc row address strobe 2 cas#[1:0] o bd16staruqp_tc column address strobe 2 mwe# o bd16staruqp_tc write enable 1 dqm[7:0] o bt8trp_tc data input/output mask 8 md[63:0] i/o bd8struqp_tc memory data 64 pci interface pci_clki i tlcht_ft 33 mhz pci input clock 1 pci_clko o bt8trp_tc 33 mhz pci output clock 1 ad[31:0] i/o bd8pciarp_ft pci address / data 32 cbe[3:0] i/o bd8pciarp_ft bus commands / byte enables 4 frame# i/o bd8pciarp_ft cycle frame 1 irdy# i/o bd8pciarp_ft initiator ready 1 trdy# i/o bd8pciarp_ft target ready 1 lock# i tlcht_ft pci lock 1 note 2 : see table 2-3 for buffer type descriptions note 3: these pins have a secondary role in that they are read by the device strap option registers during the rising edge of sysrsti#. see section 3.1 1
stpc? vega 13/86 devsel# i/o bd8pciarp_ft device select 1 stop# i/o bd8pciarp_ft stop transaction 1 par i/o bd8pciarp_ft parity signal transactions 1 serr# o bd8pciarp_ft system error 1 perr# o bd8pciarp_ft parity error 1 pci_req#[2:0] i bd8pciarp_ft pci request 3 pci_gnt#[2:0] o bd8pciarp_ft pci grant 3 pci_int#[3:0] i bd4struqp_ft pci interrupt request 4 isa control isa_clk o bt8trp_tc isa clock output multiplexer select line for ipc 1 isa_clk2x o bt8trp_tc isa clock x2 output multiplexer select line for ipc 1 osc14m o bt8trp_tc isa bus synchronisation clock 1 la[23:17] o bd8struqp_ft unlatched address 7 sa[19:0] i/o bd8struqp_ft latched address 20 sd[15:0] i/o bd8strp_ft data bus 16 ale o bd4trp_tc address latch enable 1 memr#, memw# i/o bd8struqp_ft memory read and memory write 2 smemr# 3 , smemw# 3 o bd8trp_tc system memory read and write 2 ior#, iow# i/o bd8struqp_ft i/o read and write 2 mcs16#, iocs16# i bd4struqp_ft memory and i/o chip select 16 2 bhe# o bd8struqp_ft system bus high enable 1 zws# i bd4strp_ft zero wait state (see section 2.2.4 )1 ref# o bd8trp_tc refresh cycle. 1 master# i bd4struqp_ft add on card owns bus 1 aen o bd8struqp_ft address enable 1 iochck# i bd4struqp_ft i/o channel check. 1 iochrdy i/o bd8struqp_ft i/o channel ready (isa) busy/ready (ide) 1 isaoe# o bd4strp_ft isa/ide selection 1 irq_mux[3:0] i schmitt_ft time-multiplexed interrupt request 4 dreq_mux[1:0] i bd4strp_ft time-multiplexed dma request 2 dack_enc[2:0] 3 o bd4strp_ft encoded dma acknowledge 3 tc 3 o bd4strp_ft isa terminal count 1 rtcas o bd4trp_tc real time clock address strobe 1 rmrtccs# i/o bd4strp_ft rom/rtc chip select 1 kbcs# i/o bd4strp_ft keyboard chip select 1 rtcrw# i/o bd4strp_ft rtc read/write 1 rtcds i/o bd4strp_ft rtc data strobe 1 table 2-2. defini tion of signal pins signal name dir buffer type 2 description qty note 2 : see table 2-3 for buffer type descriptions note 3: these pins have a secondary role in that they are read by the device strap option registers during the rising edge of sysrsti#. see section 3.1 1
stpc? vega 14/86 local bus (multiplexed pins) pa[24:22] 3 o bd4trp_tc address bus 3 pa[21:20], [8], [3:0] o bd4strp_ft 7 pa[18:16], [14:12] , [10], [7:4] o bd8struqp_ft 11 pa[15] o bd4trp_tc 1 pa[11] o bd8trp_tc 1 pa[9] o bd4trp_tc 1 pd[15:0] i/o bd8strp_ft data bus 16 pbe#[1] o bd8strp_ft upper byte enable (pd[15:8]) 1 pbe#[0] o bd4strup_ft lower byte enable (pd[7:0]) 1 prd# o bd4struqp_ft peripheral read control 1 pwr# o bd8trp_tc peripheral write control 1 prdy# i bd8struqp_ft data ready 1 fcs1# o bt8trp_tc flash chip select 1 fcs0# o bd4trp_tc 1 iocs#[3] o bd4strp_ft i/o chip select 1 iocs#[2:0] o bd8struqp_ft 3 ide control da[2:0] o bd8struqp_ft address bus 3 dd[15:12] i/o bd4strp_ft data bus 4 dd[11:0] i/o bd8struqp_ft 12 pcs3#,pcs1#,scs3#,scs1# o bd8struqp_ ft primary & secondary chip selects 4 diordy o bd8struqp_ft data i/o ready 1 pirq, sirq i schmitt_ft primary & secondary interrupt request 2 pdrq i schmitt_ft primary dma request 1 sdrq i bd4strp_ft secondary dma request 1 pdack#, sdack# o bd8strp_tc primary & secondary dma acknowledge 2 pdior#, sdior# o bd8strp_tc primary & secondary i/o channel read 2 pdiow#, sdiow# o bd8strp_tc primary & secondary i/o channel write 2 usb interface oc itlchtu_tc over current detect 1 usbdpls[0], usbdmns[0] i/o usbds universal serial bus port 0 2 usbdpls[1], usbdmns[1] i/o usbds universal serial bus port 1 2 poweron obt4crp usb power supply control 1 mac ethernet interface (lan) lan_txclk i bd4strp_ft transmit clock 1 lan_rxclk i bd4strp_ft receive clock 1 lan_crs i bd4strdqp_ft carrier sense indication 1 table 2-2. defini tion of signal pins signal name dir buffer type 2 description qty note 2 : see table 2-3 for buffer type descriptions note 3: these pins have a secondary role in that they are read by the device strap option registers during the rising edge of sysrsti#. see section 3.1 1
stpc? vega 15/86 lan_col i bd4strdqp_ft collision indication 1 lan_tx_en 3 o bd4strp_tc transmit enable 1 lan_txd[3:0] 3 o bd4strp_tc mii transmit data 4 lan_rx_dv i bd4strdqp_ft receive data valid 1 lan_rx_er i bd4strdqp_ft receive error 1 lan_rxd[3:0] i bd4strdqp_ft mii receive data 4 lan_mdc 3 o bd4strp_tc management data clock 1 lan_mdio i/o bd4strp_ft management data i/o 1 jtag tclk i schmitt_ft test clock 1 tdi i schmitt_ft test data input 1 tms i schmitt_ft test mode input 1 tdo o bt4trp_tc test data output 1 miscellaneous gpio[7:0] i/o bd4strp_ft general purpose i/os 8 gpio_r# 3 o bd4trp_tc gpio read signal 1 gpio_w# 3 o bd4trp_tc gpio write signal 1 uart_rxd i tlcht_ft serial port receive line 1 uart_txd 3 o bd4trp_tc serial port transmit line 1 spkrd o bd4trp_tc speaker device output 1 scl i/o bd4struqp_ft i2c interface - clock can be used for vga ddc[1] signal 1 sda i/o bd4struqp_ft i2c interface - data can be used for vga ddc[0] signal 1 scan_enable i tlchtd_tc reserved (test pin) 1 table 2-2. defini tion of signal pins signal name dir buffer type 2 description qty note 2 : see table 2-3 for buffer type descriptions note 3: these pins have a secondary role in that they are read by the device strap option registers during the rising edge of sysrsti#. see section 3.1 1
stpc? vega 16/86 table 2-3. buffer type descriptions buffer description osci13b oscillator, 13 mhz, hcmos bt4crp lvttl output, 4 ma drive capability, tri-state control bt4trp_tc lvttl output, 4 ma drive capabi lity, tri-state control, schmitt trigger bt8trp_tc lvttl output, 8 ma drive capabi lity, tri-state control, schmitt trigger bd4strp_tc lvttl bi-directional, 4 ma drive capability, schmitt trigger bd4strp_ft lvttl bi-directional, 4 ma driv e capability, schmitt trigger, 5v tolerant bd4strup_ft lvttl bi-directional, 4 ma drive c apability, schmitt trigger , pull-up, 5v tolerant bd4strdqp_ft lvttl bi-directional, 4 ma drive capab ility, schmitt trigger, pu ll-down, 5v tolerant. bd4struqp_ft lvttl bi-directional, 4 ma drive capab ility, schmitt trigger, pu ll-up, 5v tolerant. bd8strp_ft lvttl bi-directional, 8 ma driv e capability, schmitt trigger, 5v tolerant bd8strup_ft lvttl bi-directional, 8 ma drive c apability, schmitt trigger , pull-up, 5v tolerant bd8struqp_ft lvttl bi-directional, 8 ma drive capab ility, schmitt trigger, pu ll-up, 5v tolerant. bd8pciarp_ft lvttl bi-directional, 8 ma driv e capability, pci compatible, 5v tolerant bd14starp_ft lvttl bi-directional, 14 ma drive capabili ty, schmitt trigger, ieee1 284 compliant, 5v tolerant bd16staruqp_tc lvttl bi-directional, 16 ma drive capability, schmitt trigger schmitt_ft lvttl input, schmitt trigger, 5v tolerant tlcht_ft lvttl input, 5v tolerant tlchtd_tc lvttl input, pull-down tlchtu_tc lvttl input, pull-up usbds usb 1.1 compliant pad buffer for details on electrical spec ifications of the pads see table 4-3. 1
stpc? vega 17/86 2.2 signal descriptions 2.2.1 basic clocks and resets sysrsti# system reset/power good. this input is low when the reset switch is depressed. otherwise, it reflects the power supply power good signal. this input is asyn chronous to all clocks, and acts as a negative active reset. the reset circuit initiates a hard reset on the rising edge of this signal. for more details please refer to section 4.5.1 sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buffered version of this output and the pci bus reset is an externally buffered version of this output. for more details please refer to section 4.5.1 xtali 14.3 mhz crystal input xtalo 14.3 mhz crystal output. these pins are connected to the 14.318 mhz crystal to provide the reference clock for the internal frequency synthesizer to generate all remaining clocks. a 14.318 mhz series cut quartz crystal should be connected between these two pins. balance capacitors of 15 pf should also be added. in the event of an external osc illator providing the master clock signal to the stpc vega device, the ttl signal should be connected to xtali. hclk host clock. this clock supplies the cpu and the host related blocks. this clock can be doubled inside the cpu and is intended to operate in the range 25 mhz to 133 mhz. this clock is generated internally from a phase locked loop (pll) but it can be driven directly from the external system. dev_clk peripheral clock. 24 mhz general purpose peripheral clock. also known as peri_clk in the schematics. it is provided for convenience for the integration of a floppy disk driver function in an external chip. this clock signal is not available in local bus mode. 2.2.2 memory interface mclki memory clock input. this clock is used to drive the sdram controller. this input should be a buffered version of the mclko signal with the track lengths between the buffer and the pin matched with the track lengths between the buffer and the dimms. mclko memory clock output. this clock is used to drive the dimms on the board and is generated from an internal pll. the default value is 66 mhz. ma[12:0] memory address. multiplexed row and column address lines. ma[11] becomes cs2# chip select where 16 mbit devices are used. ba[1:0] memory bank address. ba[1] becomes cs3# chip select where 16 mbit devices are used. cs#[1:0] chip select. these signals are used to disable or enable device operation by masking or enabling all sdram inputs except mclk, cke and dqm. md[63:0] memory data. this is the 64-bit memory data bus. ras#[1:0] row address strobe. there are two active-low row address strobe output signals. the ras# signals drive the memory devices directly without any external buffering.this is one signal that is routed to two buffers. cas#[1:0] column address strobe. there are two active-low column address strobe output signals. the cas# signals drive the memory devices directly without any external buffering. this is one signal that is routed to two buffers. mwe# write enable. write enable specifies whether the memory access is a read (mwe# = h) or a write (mwe# = l). dqm#[7:0] data mask. makes data output hi-z after the clock and masks the sdram outputs. blocks sdram data input when dqm active. this has a granularity of 1 byte on the md lines. 2.2.3 pci interface pci_clki 33 mhz pci input clock. this signal is the pci bus clock input and should be driven from the pci_clko pin. pci_clko 33 mhz pci output clock. this is the master pci bus clock output. ad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. cbe#[3:0] bus commands / byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc vega owns the bus and outputs when the stpc vega owns the bus. 1
stpc? vega 18/86 frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc vega owns the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc vega initiates a bus cycle on the pci bus. it is used as an input during the pci cycles targeted to the stpc vega to determine when the current pci master is ready to complete the current transaction. trdy# target ready. this is the target ready signal of the pci bus. it is driven as an output when the stpc vega is the target of the current bus transaction. it is used as an input when stpc vega initiates a cycle on the pci bus. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent. devsel# i/o device select. this signal is used as an input when the stpc vega initiates a bus cycle on the pci bus to determine if a pci slave device has decoded itself to be the target of the current transaction. it is asserted as an output either when the stpc vega is the target of the current pci transaction or when no other device asserts devsel# prior to the subtractive decode phase of the current pci transaction. stop# stop transaction. stop is used to implement the disconnect, retry and abort protocol of the pci bus. it is used as an input for bus cycles initiated by the stpc vega and is used as an output when a pci master cycle is targeted to the stpc vega. par parity signal transactions. this is the parity signal of the pci bus. th is signal is used to guarantee even parity across ad[31:0], cbe#[3:0], and par. this signal is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. its assertion is identical to that of the ad bus delayed by one pci clock cycle. serr# system error. this is the system error signal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if target aborts a stpc vega initiated pci transaction. its assertion by either the stpc vega or by another pci bus agent will trigger the assert ion of nmi to the host cpu. this is an open drain output. perr# parity error. a sustained tri-state signal used to denote the detection of a parity error related to a data phase. pci_req#[2:0] pci request. these pins are the three external pci master request pins. they indicate to the pci arbiter that external agents desire the use of the bus. pci_gnt#[2:0] pci grant. these pins indicate that the pci bus has been granted to the master requesting it via pcireq#. pci_int#[3:0] pci interrupt request. these are the pci bus interrupt signals. 2.2.4 isa interface isa_clk, isa_clkx2 isa clock x1, x2. these pins generate the clock signal for the isa bus and a doubled clock signal. they are also used as the multiplexer control lines fo r the interrupt controller interrupt input lines. isa_clk is generated from either pciclk/4 or osc14m/ 2. osc14m isa bus synchronisation clock output. this is the buffered 14.318 mhz clock for the isa bus. la[23:17] unlatched address. when the isa bus is active, these pins are isa bus unlatched address lines for 16-bit devices. when the isa bus is accessed by any cycle initiated from the pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are in input mode. sa[19:0] isa address bus. system address bus of isa on 8-bit slot. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus. these pins are the external data bus to the isa bus. ale address latch enable. this is the address latch enable output of the isa bus and is asserted by stpc vega to indicate that la23-17, sa19-0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma master or an isa master cycles by the st pc vega. ale is driven low after reset. memr# memory read. this is the memory read command signal of the isa bus. it is used as an input when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an input when an isa master owns the bus and is an output at all other times. 1
stpc? vega 19/86 smemr# system memory read. the stpc vega generates the isa bus smemr# signal only when the address is below one megabyte or the cycle is a refresh cycle. smemw# system memory write. the stpc vega generates the isa bus smemw# signal only when the address is below one megabyte. ior# i/o read. this is the isa bus io read command signal. it is an input when an isa master owns the bus and is an output at all other times. iow# i/o write. this is the isa bus io write command signal. it is an input when an isa master owns the bus and is an output at all other times. mcs16# memory chip select16. this is the decode of the isa la23-17 address bus pins without any qualification of the command signal lines. mcs16# is always an input. the stpc vega ignores this signal during io and refresh cycles. iocs16# io chip select16. this signal is the decode of the isa sa15-0 address bus pins without any qualification of the command signals. the stpc vega does not drive iocs16# (similar to pc-at design). an isa master access to an internal register of the stpc vega is executed as an extended 8-bit io cycle. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being transferred on the sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. zws# zero wait state. this signal is inactif and hardwired to 1. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc vega performs a refresh cycle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a refresh cycle. the stpc vega performs a pseudo hidden refresh. it requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. the host bus is then relinquished while the refresh cycle continues on the isa bus. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. aen address enable. address enable is enabled when the dma controller is the bus owner to indicate that a dma transfer will occur. the enabling of the signal indicates to io devices to ignore the ior#/iow# signal during dma transfers. iochck# io channel check. io channel check is enabled by any isa device to signal an error condition that cannot be corrected. nmi signal becomes active upon seeing iochck# active if the corresponding bit in port b is enabled. iochrdy channel ready. iochrdy is the io channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of the stpc vega. the stpc vega monitors this signal as an input when performing an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc vega since the access to the system memory can be considerably delayed due to the uma architecture. isaoe# isa oe control. this signal controls the oe signal of the external transceiver that connects the ide dd bus and isa sa bus. set high selects the ide bus and low selects the isa bus. irq_mux[3:0] multiplexed in terrupt request. these are the isa bus interrupt signals. they have to be encoded before connection to the stpc vega using isaclk and isaclkx2 as the input selection strobes. note that irq8b, which by convention is connected to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected directly to the irq pin of the rtc. dreq_mux[1:0] isa bus multiplexed dma request. these are the isa bus dma request signals. they are to be encoded before connection to the stpc vega using isaclk and isaclkx2 as the input selection strobes. dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc vega before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. 2.2.5 x-bus interface rtcas# real time clock address strobe. this signal is asserted for any i/o write to port 70h. rmrtccs# rom/real time clock chip select. this signal is asserted if a rom access is decoded during a memory cycle. it should be 1
stpc? vega 20/86 combined with memr# or memw# signals to properly access the rom. during an io cycle, this signal is asserted if acce ss to the real time clock (rtc) is decoded. it should be combined with ior or iow# signals to properly access the real time clock. kbcs# keyboard chip select. this signal is asserted if a keyboard access is decoded during an i/o cycle. rtcrw# real time clock rw . this pin is a multi- function pin. when isaoe# is active, this signal is used as rtcrw#. this sig nal is asserted for any i/o write to port 71h. rtcds# real time clock ds . this pin is a multi- function pin. when isaoe# is active, this signal is used as rtcds. this signal is asserted for any i/ o read to port 71h. note: the rmrtccs#, kbcs#, rtcrw# and rtcds# signals must be ored externally with isaoe# and then connected to the external device. an ls244 or equivalent function can be used if oe# is connected to isaoe# and the output is provided with a weak pull-up resistor as shown in figure 6-13 . 2.2.6 local bus pa[23:0] address bus output. pd[15:0] data bus. this is the 16-bit data bus. pd[7:0] is the lsb and pd[15:8] is the msb. prd# read control output. pwr# write control output. prdy# data ready input. this signal is used to create wait states on the bus. when low, it completes the current cycle. fcs#[1:0] flash chip select output. these are the programmable chip select signals for up to two banks of flash memory. fcs0# is used for the boot process iocs#[3:0] i/o chip select output. these are the programmable chip select signals for up to eight external i/o devices. th is is possible through external logic and enabling bit 11 of the local bus control register section 11.7. of the programming manual. pbe#[1:0] byte enable. these are the byte enables that identifies on which databus the date is valid. pbe#[0] corres ponds to pd[7:0] and pbe#[1] corresponds to pd[15:8]. these are normally used when 8 bit transfers are transferred across the 16 bit bus. 2.2.7 ide interface da[2:0] address. these signals are connected to da[2:0] of ide devices directly or through a buffer. if the toggling of signals are to be masked during isa bus cycles, they can be externally ored with isaoe# before being connected to the ide devices. dd[15:0] data bus. when the ide bus is active, they serve as ide signals dd[11:0]. ide devices are connected to sa[19:8] directly and the isa bus is connected to these pins through two ls245 transceivers as described in figure 6-13 . pcs1#, pcs3# primary chip select. these signals are used as the active high primary master & slave ide chip select signals. these signals must be externally anded with the isaoe # signal before driving the ide devices to guarantee it is active only when the isa bus is idle. scs1#, scs3# secondary chip select. these signals are used as the active high secondary master & slave ide chip select signals. these signals must be externally anded with the isaoe # signal before driving the ide devices to guarantee it is active only when the isa bus is idle. diordy busy/ready. this pin serves as the ide signal diordy. pirq primary interrupt request. sirq secondary interrupt request. interrupt request from ide channels. pdrq primary dma request. sdrq secondary dma request. dma request from ide channels. pdack# primary dma acknowledge. sdack# secondary dma acknowledge. dma acknowledge to ide channels. pdior#, pdiow# primary i/o re ad & write. sdior#, sdiow# secondary i/o read & write . primary & secondary ch annel read & write. 2.2.8 usb interface oc over current detect this signal is used to monitor the status of the usb power supply lines of both devices. usb port are disabled when oc signal is asserted. usbdpls0, usbdmns0 universal serial bus data 0 this signal pair comprises the differential data signal for usb port 0. 1
stpc? vega 21/86 usbdpls1, usbdmns1 universal serial bus port 1 this signal pair comprises the differential data signal for usb port 1. poweron usb power supply lines 2.2.9 media access controller (mac) ethernet interface (lan) lan_rxclk receive clock. this input provides the timing reference for the transfer of the receive data into the device. lan_rxd[3:0] receive data. mii (media independent interface) receive data. data is sampled on every rising edge of lan_rxclk. lan_crs carrier sense shall be asserted by the physical layer (phy) when either the transmit or receive medium is non idle. lan_crs shall be de- asserted by the phy when both the transmit and receive media are idle. the phy shall ensure that lan_crs remains asserted throughout the duration of a collision condition. lan_crs is not required to transition sy nchronously with respect to either the lan_txclk or the lan_rxclk. lan_col asserted by the phy upon detection of a collision on the medi um, and shall remain asserted while the collis ion condition persists. lan_col is not required to transition synchronously with respect to either the lan_txclk or the lan_rxclk. lan_txclk transmit clock . this input provides the timing reference for the transfer of the transmit data into the device. lan_txd[3:0] transmit data. mii transmit data bus. valid data is generated on lan_txd[3:0] on every rising edge of lan_txclk while lan_tx_en is asserted. while lan_tx_en is deserted, lan_txd[3:0] values are driven to 0. lan_txd[3:0] transitions are synchronous to rising edges of lan_txclk. lan_tx_en transmit enable . indicates when the device is presenting valid transmit data on the bus. while lan_tx_en is asserted, the device generates lan_txd[3:0]. lan_tx_en is asserted with the first data of preamble and remains asserted throughout the duration of the packet until it is deserted prior to the first lan_txclk following the final data of the frame. lan_tx_en transitions are synchronous to lan_txclk. lan_rx_dv receive data valid is driven by the phy to indicate that the phy is presenting recovered and decoded nibbles on the lan_rxd[3:0] bundle and that the data on lan_rxd[3:0] is synchronous to lan_rxclk. lan_rx_dv transitions synchronously with respect to the lan_rxclk. lan_rx_dv remains asserted continuously from the first recovered nibble of the frame through the final recovered nibble and is negated prior to the first lan_rxclk that follows the final nibble. lan_rx_er receive error is driven by the phy. it shall be asserted for one or more lan_rxclk periods to indicate to the reconciliation sublayer that an error (e.g. a coding error, or any error that the phy is capable of detecting, and that may otherwise be undetectable at the mac sublayer) was detected somewhere in the frame presently being transferred from the phy to the reconciliation sublayer. lan_rx_er shall transition synchronously with respect to lan_rxclk. while lan_rx_dv is de-asserted, the phy may provide a false carrier indication by asserting the lan_rx_er signal for at least one cycle of the lan_rxclk while driving the appropriate value onto lan_rxd[3:0]. lan_mdc management data clock. non- continuous clock output that provides a timing reference for bits on the lan_mdio pin. during mii management port operations, lan_mdc minimum high and low time is 160 ns each and the minimum period for lan_mdc is 400 ns. when no management operations are in progress, lan_mdc is driven low. lan_mdio management data i/o. bi-directional mii management port data pin. lan_mdio is an output during the header portion of the management frame transfers and during the data portion of write operations. lan_mdio is an input during the data portion of read operations. 2.2.10 i 2 c scl serial clock sda serial data 2.2.11 jtag interface tclk test clock tdi test data input tms test mode input tdo test data output trst test reset input 2.2.12 miscellaneous gpio[7:0] general purpose i/os 1
stpc? vega 22/86 gpio_r# gpio read gpio_w# gpio write uart_rxd, uart_txd single uart. this rxtx only uart serial port has programmable word length, stop bits and parity and a programmable baud rate generator. it also includes an interrupt generator, a scratch register and two 16-byte fifo registers. spkrd speaker drive. this the output to the speaker and is the and of the counter 2 output with bit 1 of port 61, and drives an external speaker driver. this output should be connected to a 7407-type high voltage driver. scan_enable reserved . this pin is reserved for test and miscellaneous functions. vdd_core 1.8 v 0.15 v core power supply. these power pins are necessary to supply the core with 1.8 v. vdd_core 3.3 v 0.3 v core power supply. these power pins are necessary to supply the core with 3.3 v. 1
stpc? vega 23/86 2.3 signal detail the muxing between isa and local bus is performed by external strap options. the resulting interface is then dynamically muxed with the ide interface. . . table 2-4. isa / ide dynamic multiplexing isa bus (isaoe# = 0) ide (isaoe# = 1) rmrtccs# dd[15] kbcs# dd[14] rtcrw# dd[13] rtcds dd[12] sa[19:8] dd[11:0] la[23] scs3# la[22] scs1# la[21] pcs3# la[20] pcs1# la[19:17] da[2:0] iochrdy iordy table 2-5. isa / local bus pin sharing isa / ipc local bus sd[15:0] pd[15:0] dreq_mux[1:0] pa[21:20] smemr# pa[19] memw# pa[18] bhe# pa[17] aen pa[16] ale pa[15] memr# pa[14] ior# pa[13] iow# pa[12] ref# pa[11] iochck# pa[10] gpio_rx pa[9] zws# pa[8] sa[7:1] pa[7:1] sa[0] prdy# tc pa[0] dack_enc[2:0] iocsx#[2:0] master# prd# mcs16# pwr# isaoe# iocsx#[3] dev_clk, rtcas# fcs#[1:0] iocs16# pbe#0 smemw# pbe#1 1
stpc? vega 24/86 table 2-6. pinout pin # pin name b5 sysrseti# c5 sysrseto# b4 xtali a4 xtalo ac25 hclk f25 dev_clk/fcs#[1] ae17 mclki ad16 mclko af21 ma[0] ad20 ma[1] ae21 ma[2] ac20 ma[3] af22 ma[4] ad21 ma[5] ae22 ma[6] af23 ma[7] ac21 ma[8] ad22 ma[9] ae23 ma[10] ac22 ba[0] ad23 ma[12] ad18 cs#[0] ae19 cs#[1] ad19 ma[11]/cs#[2] af20 cs#[3]/ba[1] ac19 ras#[0] ae20 ras#[1] ad17 cas#[0] ae18 cas#[1] ae14 dqm#[0] af14 dqm#[1] ad15 dqm#[2] ae15 dqm#[3] af15 dqm#[4] ac15 dqm#[5] ae16 dqm#[6] ac16 dqm#[7] ac17 mwe# u4 md[0] v1 md[1] v2 md[2] v3 md[3] w2 md[4] for note definition see table 2-2 definition of signal pins w3 md[5] y1 md[6] y2 md[7] w4 md[8] aa1 md[9] y3 md[10] aa2 md[11] y4 md[12] ab1 md[13] aa3 md[14] ab2 md[15] aa4 md[16] ac1 md[17] ab3 md[18] ac2 md[19] ab4 md[20] ac3 md[21] ad2 md[22] ae1 md[23] ac5 md[24] ad4 md[25] ae3 md[26] af2 md[27] ac6 md[28] ad5 md[29] ae4 md[30] af4 md[31] ae5 md[32] ad6 md[33] ac7 md[34] af5 md[35] ae6 md[36] ad7 md[37] ac8 md[38] af6 md[39] ae7 md[40] ad8 md[41] af7 md[42] ae8 md[43] ad9 md[44] ac10 md[45] ae9 md[46] ad10 md[47] af9 md[48] ae10 md[49] table 2-6. pinout pin # pin name for note definition see table 2-2 definition of signal pins ac11 md[50] ad11 md[51] ae11 md[52] ac12 md[53] af11 md[54] ad12 md[55] ae12 md[56] af12 md[57] ac13 md[58] ad13 md[59] ae13 md[60] af13 md[61] ac14 md[62] ad14 md[63] aa23 pci_clki ab25 pci_clko aa24 ad[0] y23 ad[1] ab24 ad[2] aa25 ad[3] y24 ad[4] w23 ad[5] aa26 ad[6] y25 ad[7] w24 ad[8] y26 ad[9] w25 ad[10] v24 ad[11] v25 ad[12] u23 ad[13] v26 ad[14] u24 ad[15] u25 ad[16] t23 ad[17] t24 ad[18] t25 ad[19] t26 ad[20] r23 ad[21] r24 ad[22] r25 ad[23] r26 ad[24] p23 ad[25] p24 ad[26] p25 ad[27] p26 ad[28] table 2-6. pinout pin # pin name for note definition see table 2-2 definition of signal pins 1
stpc? vega 25/86 n23 ad[29] n24 ad[30] n25 ad[31] n26 cbe[0] m23 cbe[1] m24 cbe[2] m25 cbe[3] m26 frame# l26 trdy# l25 irdy# l24 stop# l23 devsel# k24 par k23 serr# j26 perr# k25 lock# j25 poweron j24 oc h25 usbdmns[0] h24 usbdpls[0] h23 usbdmns[1] g25 usbdpls[1] ad25 pci_req#[0] ac24 pci_req#[1] ae26 pci_req#[2] ae24 pci_gnt#[0] af25 pci_gnt#[1] ab23 pci_gnt#[2] d6 pci_int[0] d5 pci_int[1] c4 pci_int[2] b3 pci_int[3] b23 la[17]/da[0] c22 la[18]/da[1] d21 la[19]/da[2] a23 la[20]/pcs1# b22 la[21]/pcs3# c21 la[22]/scs1# d20 la[23]/scs3# d17 sa[0]/prdy# a18 sa[1]/pa[1] c17 sa[2]/pa[2] b17 sa[3]/pa[3] d16 sa[4]/pa[4] c16 sa[5]/pa[5] table 2-6. pinout pin # pin name for note definition see table 2-2 definition of signal pins b16 sa[6]/pa[6] a16 sa[7]/pa[7] e24 sa[8]/dd[0] d25 sa[9]/dd[1] e23 sa[10]/dd[2] d24 sa[11]/dd[3] c25 sa[12]/dd[4] b26 sa[13]/dd[5] a25 sa[14]/dd[6] b24 sa[15]/dd[7] c23 sa[16]/dd[8] d22 sa[17]/dd[9] f23 sa[18]/dd[10] d26 sa[19]/dd[11] d15 sd[0]/pd[0] c15 sd[1]/pd[1] b15 sd[2]/pd[2] a15 sd[3]/pd[3] d14 sd[4]/pd[4] c14 sd[5]/pd[5] b14 sd[6]/pd[6] a14 sd[7]/pd[7] d13 sd[8]/pd[8] c13 sd[9]/pd[9] b13 sd[10]/pd[10] a13 sd[11]/pd[11] a12 sd[12]/pd[12] b12 sd[13]/pd[13] c12 sd[14]/pd[14] d12 sd[15]/pd[15] d1 isa_clk f3 isa_clk2x e1 osc14m e2 lan_txclk f2 lan_rxclk g3 lan_crs f1 lan_col h4 lan_tx_en g2 lan_txd[0] h3 lan_txd[1] j2 lan_txd[2] h2 lan_txd[3] j3 lan_rx_dv k4 lan_rx_er k2 lan_rxd[0] table 2-6. pinout pin # pin name for note definition see table 2-2 definition of signal pins l4 lan_rxd[1] l3 lan_rxd[2] l2 lan_rxd[3] k3 lan_mdc m4 lan_mdio c11 ale/pa[15] c7 zws#/pa[8] a11 bhe#/pa[17] b10 memr#/pa[14] c10 memw#/pa[18] d10 smemr#/pa[19] a9 smemw#/pbe#1 c9 ior#/pa[13] b8 iow#/pa[12] a7 mcs16#/pwr# b7 iocs16#/pbe#0 c8 master#/prd# d8 ref#/pa[11] d11 aen/pa[16] a6 iochck#/pa[10] a22 iochrdy/iordy e26 isaoe#/iocsx#[3] b6 rtcas#/fcs#[0] g24 rtcds#/dd[12] e25 rtcrw#/dd[13] g23 rmrtccs#/dd[15] d7 lb_pa[22] a5 lb_pa[23] c6 lb_pa[24] b21 pirq c20 sirq a21 pdrq d19 sdrq b20 pdack# c19 sdack# a20 pdior# b19 pdiow# c18 sdior# b18 sdiow# a2 irq_mux[0] b9 irq_mux[1] b11 irq_mux[2] b1 irq_mux[3] c2 dreq_mux[0]/pa[20] d3 dreq_mux[1]/pa[21] table 2-6. pinout pin # pin name for note definition see table 2-2 definition of signal pins 1
stpc? vega 26/86 e4 dack_enc[0]/iocsx#[0] d2 dack_enc[1]/iocsx#[1] e3 dack_enc[2]/iocsx#[2] f4 tc/pa[0] f24 kbcs#/dd[14] p4 gpio[0] p3 gpio[1] p2 gpio[2] p1 gpio[3] r1 gpio[4] r2 gpio[5] r3 gpio[6] r4 gpio[7] t1 gpio_r#/pa[9] t2 gpio_w# g4 spkrd u3 scl t3 sda n4 scan_enable n1 tclk m1 tms m3 tdi m2 tdo n3 uart_rxd n2 uart_txd j1 vdd33_cpuclk_pll l1 vdd18_cpuclk_pll g26 vdd_dev_clk_pll 1 af18 vdd_mclk_pll 1 ab26 vdd_pciclko_pll 1 c1 vdd_core ad1 vdd_core c26 vdd_core ad26 vdd_core k1 vdd h26 vdd w1 vdd w26 vdd a3 vdd a10 vdd a17 vdd a24 vdd af3 vdd af10 vdd af17 vdd table 2-6. pinout pin # pin name for note definition see table 2-2 definition of signal pins af24 vdd f26 vss_dev_clk_pll g1 vss_cpuclk_pll ac26 vss_pciclko_pll af16 vss_mclk_pll j4 gnd v4 gnd j23 gnd v23 gnd d9 gnd d18 gnd ac9 gnd ac18 gnd h1 gnd u1 gnd k26 gnd u26 gnd a8 gnd a19 gnd af8 gnd af19 gnd a1 gnd a26 gnd b2 gnd b25 gnd c3 gnd c24 gnd d4 gnd d23 gnd ac4 gnd ac23 gnd ad3 gnd ad24 gnd ae2 gnd ae25 gnd af1 gnd af26 gnd l[11:16] gnd m[11:16] gnd n[11:16] gnd p[11:16] gnd r[11:16] gnd t[11:16] gnd t4 unconnected u2 unconnected table 2-6. pinout pin # pin name for note definition see table 2-2 definition of signal pins 1
stpc? vega 27/86 3 strap options this chapter defines the vega strap options and their locations. the logi c levels on the following dual-function pins are sampled on the rising edge of the last clk in whic h reset is active (when sysrsetix is low). all bits are read-only. table 3-1. strap options pin location setting reference lan_txd[0] index 4a, bit 0 user defined see section 3.1.1 lan_txd[1] index 4a, bit 1 lan_txd[2] index 4a, bit 2 lan_txd[3] index 4a, bit 3 lan_tx_en index 4a, bit 4 gpio_wx index 4a, bit 5 pull down gpio_rx index 4a, bit 6 pull down dack_enc[1] index 4a, bit 7 pull up lb_pa22 index 4b, bit 0 pull down see section 3.1.2 lb_pa23 index 4b, bit 1 pull up lb_pa24 index 4b, bit 2 pull down lan_mdc index 4b, bit 3 pull down uart_txd index 4b, bit 4 pull down tc index 4b, bit 5 pull up dack_enc[0] index 4b, bit 6 pull up smemrx index 4b, bit 7 pull down smemwx index 4c, bit 0 pull down see section 3.1.3 dack_enc[2] index 4c, bit 1 pull up note that all strap options must be impl emented including those t hat are user defined 1
stpc? vega 28/86 3.1 power on strap register descriptions 3.1.1 adpc strap regist er 0 configuration adpc0 access = 0022h/0023h regoffset = 04ah 7 6543210 dack_enc[1] gpio_rx gpio_wx lan_tx_en lan_txd[3] lan_txd[2] lan_txd[1] lan_txd[0] this register defaults to the values sa mpled on above dual-function pins after reset bit nb sampled mnemonic description bit 7 dack_enc[1] reflects the value sampled on dack_enc[1] pin to control the enabling of the lo- cal bus or the isa bus: 1: isa bus functionality of the device is enabled, the local bus is disabled. 0: local bus functionality of the device is enabled, the isa bus is disabled. default: strapped to logic 1. bit 6 gpio_rx reflects the value sampled on gpio_rx pin to control the source of hclk and mclko. 1: external clock source is dr iving the hclk pin, mclko pin is tristated and mclko source is external. 0: mclko and hclk pins are both outputs and are connected to their respective internal frequency synthesizer outputs. default: strapped to logic 0. bit 5 gpio_rx reflects the value sampled on gpio_wx pi n to control the clock relationship be- tween mclk and hclk. 1: mclk and hclk have the same frequency; will improve system performance. 0: mclk and hclk have different frequencies. default: strapped to logic 0. bits 4-0 lan_tx_en : lan_txd[0] reflect the values sampled on lan_tx_en and lan_txd[3:0] pins to control hclk and pci_clk frequencies. 00000: hclk = 24.928974 mhz; pci_clk = 12.46 mhz; 00001: hclk = 49.857948 mhz; pci_clk = 24.93 mhz; 00010: hclk = 66.634607 mhz; pci_clk = 33.32 mhz; 00011: hclk = 72.485786 mhz; pci_clk = 24.16 mhz; 00100: hclk = 74.895095 mhz; pci_clk = 24.97 mhz; 00101: hclk = 77.448337 mhz; pci_clk = 25.82 mhz; 00110: hclk = 79.943172 mhz; pci_clk = 26.65 mhz; 00111: hclk = 82.329535 mhz; pci_clk = 27.44 mhz; 01000: hclk = 87.499989 mhz; pci_clk = 29.17 mhz; 01001: hclk = 89.999989 mhz; pci_clk = 30.00 mhz; 01010: hclk = 92.471579 mhz; pci_clk = 30.82 mhz; 01011: hclk = 97.473764 mhz; pci_clk = 32.49 mhz; 01100: hclk = 99.715896 mhz; pci_clk = 33.24 mhz; 01101: hclk = 102.430057 mhz; pci_clk = 25.61 mhz; 01110: hclk = 104.999987 mhz; pci_clk = 26.25 mhz; 01111: hclk = 107.386350 mhz; pci_clk = 26.85 mhz; 10000: hclk = 109.989655 mhz; pci_clk = 27.50 mhz; 10001: hclk = 112.499986 mhz; pci_clk = 28.12 mhz; 10010: hclk = 114.545440 mhz; pci_clk = 28.64 mhz; 10011: hclk = 117.409076 mhz; pci_clk = 29.35 mhz; 10100: hclk = 119.914757 mhz; pci_clk = 29.98 mhz; 10101: hclk = 122.499984 mhz; pci_clk = 30.62 mhz; 10110: hclk = 124.958662 mhz; pci_clk = 31.24 mhz; 10111: hclk = 127.431802 mhz; pci_clk = 31.86 mhz; 11000: hclk = 129.965018 mhz; pci_clk = 32.49 mhz; 11001: hclk = 133.269214 mhz; pci_clk = 33.32 mhz; 1
stpc? vega 29/86 3.1.2 adpc strap regist er 1 configuration adpc1 access = 0022h/0023h regoffset = 04bh 7 6543210 smemrx dack_enc[0] tc uart_txd lan_mdc lb_pa24 lb_pa23 lb_pa22 this register defaults to t he values sampled on the above dual-function pins after reset bit nb sampled mnemonic description bit 7 smemrx reserved default: st rapped to logic 0 bit 6 dack_enc[0] reserved default: st rapped to logic 1. bit 5 tc reserved, default: strapped to logic 1. bits 4-3 uart_txd: lan_mdc reflect the values sampled on uart_txd and lan_mdc pins to con- trol the uide clock in conjunction with hclko_strap[4:0] (bits 4-0 of index register 4a - para section 3.1.1 ) details are given in table 3.1.3 . bits 2-0 lb_pa24: lb_pa22 reflect the values sampled on lb_pa24, lb_pa23 and lb_pa22 pins to control the bus to core clo ck multiplication factor of cp250c. 000: ratio of 2.5x 010: ratio of 2x 001: ratio of 3x 011: ratio of 3.5x 1xx: reserved default: strapped to logic 010. 1
stpc? vega 30/86 table 3-2. hclk, pciclk an d uideclk frequencies (mhz) hclk pciclk uideclk hlck strap settings bits [4:0] freq freq div factor uideclk33 (uideclk_strap=10) uideclk66 (uideclk_strap=00) uideclk100 (uideclk_strap=11) freq div factor freq div factor freq div factor 00h 24.93 12.46 2.0 16.62 * 1 .5 16.62 * 1.5 24.93 * 1.0 01h 49.86 24.93 2.0 33.24 1. 5 33.24 * 1.5 49.86 * 1.0 02h 66.63 33.32 2.0 33.32 2. 0 66.63 1.0 66.63 * 1.0 03h 72.49 24.16 3.0 28.99 2. 5 48.32 1.5 72.49 1.0 04h 74.90 24.97 3.0 29.96 2. 5 49.93 1.5 74.90 1.0 05h 77.45 25.82 3.0 30.98 2. 5 51.63 1.5 77.45 1.0 06h 79.94 26.65 3.0 31.98 2. 5 53.30 1.5 79.94 1.0 07h 82.33 27.44 3.0 32.93 2. 5 54.89 1.5 82.33 1.0 08h 87.50 29.17 3.0 29.17 3. 0 58.33 1.5 87.50 1.0 09h 90.00 30.00 3.0 30.00 3. 0 60.00 1.5 90.00 1.0 0ah 92.47 30.82 3.0 30.82 3.0 61.65 1.5 92.47 1.0 0bh 97.47 32.49 3.0 32.49 3.0 64.98 1.5 97.47 1.0 0ch 99.72 33.24 3.0 33.24 3.0 66.48 1.5 99.72 1.0 0dh 102.43 25.61 4.0 25.61 4.0 51.22 2.0 68.29 1.5 0eh 105.00 26.25 4.0 26.25 4.0 52.50 2.0 70.00 1.5 0fh 107.39 26.85 4.0 26.85 4.0 53.69 2.0 71.59 1.5 10h 109.99 27.50 4.0 27.50 4.0 54.99 2.0 73.33 1.5 11h 112.50 28.12 4.0 28.12 4.0 56.25 2.0 75.00 1.5 12h 114.55 28.64 4.0 28.64 4.0 57.27 2.0 76.37 1.5 13h 117.41 29.35 4.0 29.35 4.0 58.70 2.0 78.27 1.5 14h 119.91 29.98 4.0 29.98 4.0 59.96 2.0 79.94 1.5 15h 122.50 30.62 4.0 30.62 4.0 61.25 2.0 81.67 1.5 16h 124.96 31.24 4.0 31.24 4.0 62.48 2.0 83.31 1.5 17h 127.43 31.86 4.0 31.86 4.0 63.72 2.0 84.95 1.5 18h 129.97 32.49 4.0 32.49 4.0 64.98 2.0 86.65 1.5 19h 133.27 33.32 4.0 33.32 4.0 66.63 2.0 88.85 1.5 1
stpc? vega 31/86 3.1.3 adpc strap register 2 configuration adpc2 access = 0022h/0023h regoffset = 04ch 765432 1 0 rsv dack_enc[2] smemwx this register defaults to the values samp led on the above dual-function pins after reset bit number sampled mnemonic description bits 7-2 rsv reserved bit 1 dack_enc[2] reflects the value sampled on dack _enc[2] pin to control he local bus 8/16 bit boot flash width(localbus_bk0_width). 0: 8-bit width 1: 16-bit width. bit 0 smemwx reflects the value sampled on smem wx pin to control the enabling of mclki pll. 1: the mclki pll is bypassed. 0: the mclki pll is enabled. default: strapped to logic 0. 1
stpc? vega 32/86 4 electrical specifications 4.1 introduction the electrical specifications in this chapter are val- id for the stpc vega. 4.2 electrical connections 4.2.1 power/ground connections/ decoupling due to the high frequency of operation of the stpc vega, it is necessar y to install and test this device using standard high frequency techniques. the high clock frequencies used in the stpc vega and its output buffer circuits can cause tran- sient power surges when several output buffers switch output levels simultaneously. these effects can be minimized by filtering the dc power leads with low-inductance dec oupling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 4.2.2 unused input pins all inputs not used by the designer and not listed in the table of pin connections in chapter 3 should be connected either to vdd or to vss. connect ac- tive-high inputs to vdd through a 20 k ? (10%) pull-up resistor and active-low inputs to vss and connect active-low inputs to vcc through a 20 k ? (10%) pull-down resistor to prevent spurious op- eration. 4.2.3 reserved designated pins pins designated reserved should be left discon- nected. connecting a reserved pin to a pull-up re- sistor, pull-down resistor or an active signal could cause unexpected results and possible circuit mal- functions. 4.3 absolute maximum ratings the following table lists the absolute maximum rat- ings for the stpc vega device. stresses beyond those listed under table 4-1 limits may cause per- manent damage to the device. these are stress ratings only and do not imply that operation under any conditions other than those specified in sec- tion 14.4 ?operating conditions?. exposure to con- ditions beyond table 4-1 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of fail- ure. prolonged exposure to conditions at or near the absolute maximum ratings ( table 4-1 ) may also result in reduced useful life and reliability. note 1: the figures specified apply to an stpc device that is soldered to a board, as detailed in the board lay- out section. table 4-1. absolute maximum ratings symbol parameter minimum maximum units v ddx dc supply voltage -0.3 4.0 v v core dc supply voltage for core -0.3 1.95 v v i , v o digital input and output voltage -0.3 vdd + 0.5 v v 5t 5 volt tolerance -0.3 5.5 v v esd esd capacity (human body mode) 2000 v t stg storage temperature -40 +150 c t oper operating temperature (tcase) see note 1. -40 +105 c p tot total power dissipation of the package 5 w 1
stpc? vega 33/86 4.4 dc characteristics table 4-3. pad buffers dc characteristics table 4-4. 1.8v power consumption table 4-2. dc characteristics symbol parameter test conditions min typ max unit v dd 3.3v operating voltage 3.0 3.3 3.6 v v core 1.8v operating voltage 1.65 1.8 1.95 v p dd 3.3v supply power 3.0v < v dd < 3.6v w p core 1.8v supply power w v il input low voltage except xtali -0.3 0.8 v xtali -0.3 0.8 v v ih input high voltage except xtali 2.1 v dd +0.3 v xtali 2.35 v dd +0.3 v i lk input leakage current input, i/o -5 5 a integrated pull up/down 50 k ? buffer type i/o count io type v ih min (v) v il max (v) v oh min (v) v ol max (v) i ol min (ma) i oh max (ma) c load max (pf) derating (ps/pf) 1 c in (pf) ana 1 i - - - - - - - - - bd4strdqp_ft 8 i/o 1,4 1,4 2,64 0,06 - - - - - bd4strp_ft 23 i/o 1,1 1,34 2,65 0,06 - - - - - bd4strp_tc 9 i/o 1,06 1,31 2,65 0,06 - - - - - bd4struqp_ft 10 i/o 1,1 1,27 2,64 0,06 - - - - - bd4trp_tc 9 i/o 1,35 1,68 2,64 0,06 - - - - - bd8pciarp_ft 50 i/o 0,96 1,12 2,64 0,06 - - - - - bd8strp_ft 16 i/o 1,25 1,31 2,64 0,06 - - - - - bd8strp_tc 8 i/o 1,18 1,32 2,64 0,06 - - - - - bd8struqp_ft 33 i/o 1,12 1,27 2,64 0,06 - - - - - bd8struqp_tc 65 i/o 1,18 1,26 2,64 0,06 - - - - - bd8trp_tc 3 i/o 1,29 1,7 2,64 0,06 - - - - - bd16staruqp_tc 20 i/o 1,17 1,29 2,64 0,06 - - - - - bt4crp 1 o - - - - - - - - - bt4tr_tc 1 o - - 2,64 0,06 - - - - - bt8trp_tc 15 o - - 2,64 0,06 - - - - - osci13b 1 o - - - - - - - - - shmitt_ft 10 i 1,4 1,29 - - - - - - - tlcht_ft 3 i 1,29 1,66 - - - - - - - tlcht_tc 1 i 1,29 1,71 - - - - - - - tlchtd_tc 1 i - - - - - - - - - tlchtu_tc 1 i 1,29 1,64 - - - - - - - usbds 4 i 1,01 1,28 2,64 0,06 - - - - - note 1: time to output vari ation depending on the capacitive load. hclk (mhz) cpuclk (mhz) mclk (mhz) mode p max (mw) p typ p max 66 133 (x2) 66 sync 1.31 1.87 90 180 (x2) 90 sync 1.64 2.34 66 200 (x3) 100 async 1.77 2.51 100 200 (x2) 100 sync 1.77 2.52 1
stpc? vega 34/86 4.5 ac characteristics table 4-5 through table 4-12 list the ac charac- teristics including output delays, input setup re- quirements, input hold requirements and output float delays. these measurements are based on the measurement points identified in figure 4-1 . and figure 4-2 . the rising clock edge reference level vref and other reference levels are shown in table 4-5 for the stpc vega. input or output signals must cross these levels during testing. figure 4-1 . shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, de- fining the smallest acceptable sampling window a synchronous input signal must be stable for cor- rect operation. note: refer to figure 4-1 . figure 4-1. drive level and measurement points for switching characteristics table 4-5. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 3.0 v v ild 0.0 v clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd 1
stpc? vega 35/86 figure 4-2. clk timing measurement points clk t5 t4 t3 v ref v il (max) v ih (min) t2 t1 legend: t1 - one clock cycle t2 - minimum time at v ih t3 - minimum time at v il t4 - clock fall time t5 - clock rise time note: all signals are sampled on the rising edge of the clk. 1
stpc? vega 36/86 4.5.1 power on sequence figure 4-3 describes the power-on sequence of the stpc, also called cold reset. there is no dependency between the different power supplies and there is no constraint on their rising time. sysrsti# has no constraint on its rising edge but must stay active until power supplies are all within specifications, a margin of 10 s is even recom- mended to let the stpc plls and strap options stabilize. strap options are continuously sampled during sysrsti# low and must remain stable. once sysrsti# is high, they must not change un- til sysrsto# goes high. bus activity starts only few clock cycles after the release of sysrsto#. th e toggling signals de- pend on the stpc configuration. in isa mode, activity is visible on pci prior to the isa bus as the controller is part of the south bridge. in local bus mode, the pci bus is not accessed and the flash chip select is the control signal to monitor. figure 4-3. power-on timing diagram strap options power supplies sysrsti# sysrsto# 14 mhz 1.6 v valid configuration > 10 us hclk pci_clk 2.3 ms isaclk 1
stpc? vega 37/86 4.5.2 reset sequence figure 4-4 describes the reset sequence of the stpc, also called warm reset. the constraints on the strap options and the bus activities are the same as for the cold reset. the sysrsti# pulse duration must be long enough to have all the st rap options stabilized and must be adjusted depending on resistor values. it is mandatory to have a clean reset pulse without glitches as the stpc c ould then sample invalid strap option setting and enter into an unpredicta- ble mode. while sysrsti# is active , the pci clock pll runs in open loop mode at a speed of few 100?s khz. figure 4-4. reset timing diagram strap options sysrsti# sysrsto# 14 mhz valid configuration hclk pci_clk 2.3 ms isaclk 1.6 v md[63:0] 1
stpc? vega 38/86 4.5.3 sdram interface figure 4-5 , table 4-6 lists the ac characteristics of the sdram interface. the mclkx clocks are the input clock of the sdram devices. figure 4-5. synchronous read cycle for correct operation, the programmable read clock delay (rdclk) must not be activated. table 4-6. sdram bus ac timings name parameter min typ max unit tcycle mclki cycle time tbd tbd ns thigh mclki high time tbd tbd ns tlow mclki low time tbd tbd ns mclki rising time tbd tbd ns mclki falling time tbd tbd ns tdelay mclkx to mclki delay -0,5 2 ns toutput mclki to ras # valid 1.7 2.4 ns mclki to cas # valid 1.0 1.5 ns mclki to cs # valid 0.5 1.3 ns mclki to dqm[ ] outputs valid 0.7 1.8 ns mclki to md[ ] outputs valid 0.6 1.5 ns mclki to ma[ ] outputs valid 1.2 1.9 ns mclki to mwe # valid 1.4 2.2 ns tsetup md[63:0] setup to mckli 1.9 2.3 ns thold md[63:0] hold from mckli 3.6 4.7 ns note: these timings are for a load of 50pf. mclki stpc.output stpc.input mclkx t delay t setup t hold t output (min) t output (max) t cycle t high t low 1
stpc? vega 39/86 4.5.4 pci interface figure 4-6 and table 4-7. list the ac characteris- tics of the pci interface. pciclkx stands for any pci device clock input. figure 4-6. pci timing diagram table 4-7. pci bus ac timings name parameter min typ max unit hclk to pciclko delay (md[30:27] = 0000) 4,30 - 5,50 ns thclk hclk to pciclki delay - 6 - ns tclkx pciclki to pciclkx skew -0.5 0 0.5 ns tcycle pciclki cycle time 30 ns thigh pciclki high time 13 ns tlow pciclki low time 13 ns pciclki rising time 1.5 ns pciclko to pciclki delay 0,5 - 1,8 ns note: these timings are for a load of 50pf. pciclki stpc.output stpc.input pciclkx t clkx t setup t hold t output (min) t output (max) t cycle t high t low hclk t hclk 1
stpc? vega 40/86 4.5.5 ipc interface table 4-8 lists the ac characteristics of the ipc in- terface. figure 4-7. ipc timing diagram table 4-8. ipc interface ac timings name parameter min max unit t setup irq_mux[3:0] input setup to isaclk2x 0 - ns t setup dreq_mux[1:0] input setup to isaclk2x 0 - ns isaclk irq_mux[3:0] dreq_mux[1:0] isaclk2x t dly t setup t setup 1
stpc? vega 41/86 4.5.6 isa interface ac timing characteristics figure 4-8 and table 4-9 list the ac characteristics of the isa interface. figure 4-8. isa cycle (ref table 4-9. ) note 1: stands for smemr#, smemw# , memr#, memw#, ior# & iow#. the clock has not been represented as it is dependent on the isa slave mode. table 4-9. isa bus ac timing name parameter min max units 2 la[23:17] valid before ale# negated 5t cycles 3 la[23:17] valid before memr#, memw# asserted 3a memory access to 16-bit isa slave 5t cycles 3b memory access to 8-bit isa slave 5t cycles 9 sa[19:0] & sbhe valid before ale# negated 1t cycles 10 sa[19:0] & sbhe valid before memr#, memw# asserted 10a memory access to 16-bit isa slave 2t cycles 10b memory access to 8-bit isa slave 2t cycles 10 sa[19:0] & shbe valid before smemr#, smemw# asserted 10c memory access to 16-bit isa slave 2t cycle 10d memory access to 8-bit isa slave 2t cycle note: the signal numbering refers to figure 4-8 valid aenx valid address valid address, sbhe* v.dat a valid data 54 28 26 64 59 58 55 28 23 61 48 47 26 23 57 27 24 42 41 10 11 34 33 3 22 56 29 25 9 18 2 12 38 37 15 14 13 12 ale aen la [23:17] sa [19:0] control (note 1) iocs16# mcs16# iochrdy read data write data 1
stpc? vega 42/86 10e sa[19:0] & sbhe valid before ior#, iow# asserted 2t cycles 11 isaclk2x to iow# valid 11a memory access to 16-bit isa slave - 2bclk 2t cycles 11b memory access to 16-bit isa slave - standard 3bclk 2t cycles 11c memory access to 16-bit isa slave - 4bclk 2t cycles 11d memory access to 8-bit isa slave - 2bclk 2t cycles 11e memory access to 8-bit isa slave - standard 3bclk 2t cycles 12 ale# asserted before ale# negated 1t cycles 13 ale# asserted before memr#, memw# asserted 13a memory access to 16-bit isa slave 2t cycles 13b memory access to 8-bit isa slave 2t cycles 13 ale# asserted before smemr#, smemw# asserted 13c memory access to 16-bit isa slave 2t cycles 13d memory access to 8-bit isa slave 2t cycles 13e ale# asserted before ior#, iow# asserted 2t cycles 14 ale# asserted before al[23:17] 14a non compressed 15t cycles 14b compressed 15t cycles 15 ale# asserted before memr#, memw#, smemr#, smemw# negated 15a memory access to 16-bit isa slave- 4 bclk 11t cycles 15e memory access to 8-bit i sa slave- standard cycle 11t cycles 18a ale# negated before la[23:17] invalid (non compressed) 14t cycles 18a ale# negated before la[23:17] invalid (compressed) 14t cycles 22 memr#, memw# asserted before la[23:17] 22a memory access to 16-bit isa slave. 13t cycles 22b memory access to 8-bit isa slave. 13t cycles 23 memr#, memw# asserted before memr#, memw# negated 23b memory access to 16-bit isa slave standard cycle 9t cycles 23e memory access to 8-bit isa slave standard cycle 9t cycles 23 smemr#, smemw# asserted before smemr#, smemw# negated 23h memory access to 16-bit isa slave standard cycle 9t cycles 23l memory access to 16-bit isa slave standard cycle 9t cycles 23 ior#, iow# asserted before ior#, iow# negated 23o memory access to 16-bit isa slave standard cycle 9t cycles 23r memory access to 8-bit isa slave standard cycle 9t cycles 24 memr#, memw# asserted before sa[19:0] 24b memory access to 16-bit isa slave standard cycle 10t cycles 24d memory access to 8-bit isa slave - 3blck 10t cycles 24e memory access to 8-bit isa slave standard cycle 10t cycles 24f memory access to 8-bit isa slave - 7bclk 10t cycles 24 smemr#, smemw# asserted before sa[19:0] 24h memory access to 16-bit isa slave standard cycle 10t cycles 24i memory access to 16-bit isa slave - 4bclk 10t cycles 24k memory access to 8-bit isa slave - 3bclk 10t cycles table 4-9. isa bus ac timing name parameter min max units note: the signal numbering refers to figure 4-8 1
stpc? vega 43/86 24l memory access to 8-bit isa slave standard cycle 10t cycles 24 ior#, iow# asserted before sa[19:0] 24o i/o access to 16-bit isa slave standard cycle 19t cycles 24r i/o access to 16-bit isa slave standard cycle 19t cycles 25 memr#, memw# asserted before next ale# asserted 25b memory access to 16-bit isa slave standard cycle 10t cycles 25d memory access to 8-bit isa slave standard cycle 10t cycles 25 smemr#, smemw# asserted before next ale# asserted 25e memory access to 16-bit isa slave - 2bclk 10t cycles 25f memory access to 16-bit isa slave standard cycle 10t cycles 25h memory access to 8-bit isa slave standard cycle 10t cycles 25 ior#, iow# asserted before next ale# asserted 25i i/o access to 16-bit isa slave standard cycle 10t cycles 25k i/o access to 16-bit isa slave standard cycle 10t cycles 26 memr#, memw# asserted before next memr#, memw# asserted 26b memory access to 16-bit isa slave standard cycle 12t cycles 26d memory access to 8-bit isa slave standard cycle 12t cycles 26 smemr#, smemw# asserted before next smemr#, smemw# asserted 26f memory access to 16-bit isa slave standard cycle 12t cycles 26h memory access to 8-bit isa slave standard cycle 12t cycles 26 ior#, iow# asserted before next ior#, iow# asserted 26i i/o access to 16-bit isa slave standard cycle 12t cycles 26k i/o access to 8-bit isa slave standard cycle 12t cycles 28 any command negated to memr#, smemr#, memr#, smemw# asserted 28a memory access to 16-bit isa slave 3t cycles 28b memory access to 8-bit isa slave 3t cycles 28 any command negated to ior#, iow# asserted 28c i/o access to isa slave 3t cycles 29a memr#, memw# negated before next ale# asserted 1t cycles 29b smemr#, smemw# negated before next ale# asserted 1t cycles 29c ior#, iow# negated before next ale# asserted 1t cycles 33 la[23:17] valid to iochrdy negated 33a memory access to 16-bit isa slave - 4 bclk 8t cycles 33b memory access to 8-bit isa slave - 7 bclk 14t cycles 34 la[23:17] valid to read data valid 34b memory access to 16-bit isa slave standard cycle 8t cycles 34e memory access to 8-bit isa slave standard cycle 14t cycles 37 ale# asserted to iochrdy# negated 37a memory access to 16-bit isa slave - 4 bclk 6t cycles 37b memory access to 8-bit isa slave - 7 bclk 12t cycles 37c i/o access to 16-bit isa slave - 4 bclk 6t cycles 37d i/o access to 8-bit isa slave - 7 bclk 12t cycles 38 ale# asserted to read data valid 38b memory access to 16-bit i sa slave standard cycle 4t cycles table 4-9. isa bus ac timing name parameter min max units note: the signal numbering refers to figure 4-8 1
stpc? vega 44/86 38e memory access to 8-bit isa slave standard cycle 10t cycles 38h i/o access to 16-bit isa slave standard cycle 4t cycles 38l i/o access to 8-bit isa slave standard cycle 10t cycles 41 sa[19:0] sbhe valid to iochrdy negated 41a memory access to 16-bit isa slave 6t cycles 41b memory access to 8-bit isa slave 12t cycles 41c i/o access to 16-bit isa slave 6t cycles 41d i/o access to 8-bit isa slave 12t cycles 42 sa[19:0] sbhe valid to read data valid 42b memory access to 16-bit isa slave standard cycle 4t cycles 42e memory access to 8-bit isa slave standard cycle 10t cycles 42h i/o access to 16-bit isa slave standard cycle 4t cycles 42l i/o access to 8-bit isa slave standard cycle 10t cycles 47 memr#, memw#, smemr#, smemw#, ior#, iow# asserted to iochrdy negated 47a memory access to 16-bit isa slave 2t cycles 47b memory access to 8-bit isa slave 5t cycles 47c i/o access to 16-bit isa slave 2t cycles 47d i/o access to 8-bit isa slave 5t cycles 48 memr#, smemr#, ior# asserted to read data valid 48b memory access to 16-bit i sa slave standard cycle 2t cycles 48e memory access to 8-bit isa slave standard cycle 5t cycles 48h i/o access to 16-bit isa slave standard cycle 2t cycles 48l i/o access to 8-bit isa slave standard cycle 5t cycles 54 iochrdy asserted to read data valid 54a memory access to 16-bit isa slave 1t(r)/2t(w) cycles 54b memory access to 8-bit isa slave 1t(r)/2t(w) cycles 54c i/o access to 16-bit isa slave 1t(r)/2t(w) cycles 54d i/o access to 8-bit isa slave 1t(r)/2t(w) cycles 55a iochrdy asserted to memr#, memw#, smemr#, smemw#, ior#, iow# negated 1t cycles 55b iochry asserted to memr#, smemr# negated (refresh) 1t cycles 56 iochrdy asserted to next ale# asserted 2t cycles 57 iochrdy asserted to sa[19:0], sbhe invalid 2t cycles 58 memr#, ior#, smemr# negated to read data invalid 0t cycles 59 memr#, ior#, smemr# negated to data bus float 0t cycles 61 write data before memw# asserted 61a memory access to 16-bit isa slave 2t cycles 61b memory access to 8-bit isa slave (byte copy at end of start) 2t cycles 61 write data before smemw# asserted 61c memory access to 16-bit isa slave 2t cycles 61d memory access to 8-bit isa slave 2t cycles 61 write data valid before iow# asserted 61e i/o access to 16-bit isa slave 2t cycles 61f i/o access to 8-bit isa slave 2t cycles table 4-9. isa bus ac timing name parameter min max units note: the signal numbering refers to figure 4-8 1
stpc? vega 45/86 64a memw# negated to write data invalid - 16-bit 1t cycles 64b memw# negated to write data invalid - 8-bit 1t cycles 64c smemw# negated to write data invalid - 16-bit 1t cycles 64d smemw# negated to write data invalid - 8-bit 1t cycles 64e iow# negated to write data invalid 1t cycles 64f memw# negated to copy data float , 8-bit isa slave, odd byte by isa master 1t cycles 64g iow# negated to copy data float, 8-bit isa slave, odd byte by isa master 1t cycles table 4-9. isa bus ac timing name parameter min max units note: the signal numbering refers to figure 4-8 1
stpc? vega 46/86 4.5.7 local bus interface figure 4-9 to figure 4-12 and table 4-11 list the ac characteristics of the local bus interface. figure 4-9. synchronous read cycle figure 4-10. asynchronous read cycle pa[ ] bus csx# prd#[1:0] pd[15:0] hclk t setup t active t hold pa[ ] bus csx# prd#[1:0] pd[15:0] hclk t setup t end t hold prdy 1
stpc? vega 47/86 figure 4-11. synchronous write cycle figure 4-12. asynchronous write cycle pa[ ] bus csx# pwr#[1:0] pd[15:0] hclk t setup t active t hold pa[ ] bus csx# pwr#[1:0] pd[15:0] hclk t setup t end t hold prdy 1
stpc? vega 48/86 the table 4-10. below refers to vh, va, vs which are the register value for setup time, active time and hold time, as described in the programming manual. table 4-10. local bus cycle lenght cycle t setup t active t hold t end unit memory (fcsx#) 4 + vh 2 + va 4 + vs 4 hclk peripheral (iocsx#) 8 + vh 3 + va 4 + vs 4 hclk table 4-11. local bus interface ac timing name parameters min max units hclk to pa bus - 15 ns hclk to pd bus - 15 ns hclk to fcs#[1:0] - 15 ns hclk to iocs#[3:0] - 15 ns hclk to pwr#[1:0] - 15 ns hclk to prd#[1:0] - 15 ns pd[15:0] input setup to hclk - 4 ns pd[15:0] input hold to hclk 2 - ns prdy input setup to hclk - 4 ns prdy input hold to hclk 2 - ns 1
stpc? vega 49/86 4.5.8 usb interface the usb interface integrated into the stpc de- vice is compliant with the usb 1.1 standard. 4.5.9 jtag interface figure 4-13 and table 4-12 list the ac character- istics of the jtag interface. figure 4-13. jtag timing diagram table 4-12. jtag ac timings name parameter min max unit treset trst pulse width 1 tcycle tcycle tclk period 400 ns tclk rising time 20 ns tclk falling time 20 ns tjset tms setup time 200 ns tjhld tms hold time 200 ns tjset tdi setup time 200 ns tjhld tdi hold time 200 ns tjout tclk to tdo valid 30 ns tpset stpc pin setup time 30 ns tphld stpc pin hold time 30 ns tpout tclk to stpc pin valid 30 ns tck stpc.input trst t reset t cycle stpc.output tms,tdi tdo t jset t jhld t jout t pset t phld t pout 1
stpc? vega 50/86 4.5.10 i 2 c interface figure 4-14 and table 4-13. lists the ac typical characteristics of the i2c interface. all timings are measured when the stpc vega operate as mas- ter. table 4-13. i2c ac timings figure 4-14. i2c timing diagram. master parameter symbol standard-mode fast-mode unit typical value typical value scl clock frequency. f scl 103 390 khz hold time start condition. t hd;sta 9,5 1,8 s low period of the scl clock. t low 4,9 1,5 s high period of the scl clock. t high 4,2 1,12 s set-up time for a repeated start condition. t su;sta 9,5 1,63 s data hold time. t hd;dat 212 380 ns data set-up time. t su;dat 51,38s rise time of scl and sda signals. t r 800 152 ns fall time of scl and sda signals. t f 25 38 ns set-up time for stop condition. t su;sto 308 312 ns bus free time between a stop and start condition t buf 70 17,44 s 1
stpc? vega 51/86 5 mechanical data 5.1 388-pin package dimensions the pin numbering for the stpc 388-pin plastic bga package is shown in figure 5-1 . dimensions are shown in figure 5-2 , table 5-1. and figure 5-3 , table 5-2. . figure 5-1. 388-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2 4 6 8 10 12 14 16 18 20 22 24 26 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2 4 6 8 101214161820222426 1
stpc? vega 52/86 figure 5-2. 388-pin pbga package - pcb dimensions table 5-1. 388-pin pbga package - pcb dimensions symbols mm inches min typ max min typ max a 34.95 35.00 35.05 1.375 1.378 1.380 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.58 0.63 0.68 0.023 0.025 0.027 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail a1 ball pad corner d f e g c 1
stpc? vega 53/86 figure 5-3. 388-pin pbga package - dimensions table 5-2. 388-pin pbga package - dimensions symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g 1
stpc? vega 54/86 5.2 388-pin package thermal data the 388-pin pbga package has a power dissipation capability of 4.5w. this increases to 6w when used with a heatsink. the structure in shown in figure 5-4 . thermal dissipation opti ons are illustrated in figure 5-5 and figure 5-6 . figure 5-4. 388-pin pbga structure figure 5-5. thermal dissipation without heatsink thermal balls power & ground layers signal layers ambient board case junction board ambient ambient case junction board rca rjc rjb rba 66 125 8.5 rja = 13 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centrecentre b a 1
stpc? vega 55/86 figure 5-6. thermal dissipation with heatsink board ambient case junction board ambient ambient case junction board rca rjc rjb rba 36 50 8.5 rja = 9.5 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices heat sink is 11.1c/w 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centre balls 1
stpc? vega 56/86 5.3 soldering recommendations high quality, low defe ct soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. the heating and cooling rise rates must be compatible with the solder paste and components. a typical profile consists of a preheat, dryout, reflow and cooling sections. the most critical parameter in the preheat section is to minimize the rate of temperature rise to less than 2 c / second, in order to minimize thermal shock on the semi-conductor components. dryout section is used primarily to ensure that the solder paste is fully dried before hitting reflow temperatures. solder reflow is accomplished in the reflow zone , where the solder paste is elevated to a temperature greater than the melting point of the solder. melting temperature must be exceeded by approximately 20 c to ensure quality reflow. in reality the profile is not a line, but rather a range of temperatures all solder joints must be exposed. the total temperature deviation from component thermal mismatch, oven loading and oven uniformity must be within the band. figure 5-7. reflow soldering temperature range temperature ( c ) time ( s ) preheat dryout reflow cooling 240 0 250 200 150 100 50 0 1
stpc? vega 57/86 6 design guidelines 6.1 typical applications the stpc vega is well su ited for many display- less applications or together with a pci graphics/ video device. some of the possible implementations are described below. 6.1.1 file server a file server is a mac ethernet hot-pluggable system that enables the user to obtain additional disk capacity with great flexibility. figure 6-1. file server 6.1.2 graphics terminal an external graphics accelerator can be added to the stpc vega on the pci interface in order to take advantage of specific graphics requirements and added integration of the stpc vega figure 6-2. graphics terminal stpc vega sdram 64 flash mac 16 pci uide usb gpio i 2 c stpc vega sdram 64 flash mac 16 pci uide usb gpio i 2 c external graphics accelerator 1
stpc? vega 58/86 6.2 stpc configuration the stpc is a very flexible product with decoupled clock domains and strap options enabling a user-optimized configuration. as some trade-offs are often necessary, it is important to do an analysis of the application needs prior to design a system based on this product. the application constraints are usually the following: - cpu performance - graphics / video performance - power consumption - pci bandwidth - booting time - emc some other elements can help to tune the choice: - code size of cpu consuming tasks - data size and location on the stpc side, the configurable parameters are the following: - synchronous / asynchronous mode - hclk speed - mclk speed - cpu clock ratios (x2,x2.5, x3, x3.5) - local bus / isa bus 6.2.1 local bus / isa bus the selection between the isa bus and the local bus is relatively simple. the first one is a standard bus but slow. the local bus is fast and programmable but doesn't support any dma nor external master mechanisms. table 6-1 below summarizes the selection: before implementing a function requiring dma capability on the isa bus, it is recommended to check if it exists on pci, or if it can be implemented differently, in order to use the local bus mode. 6.2.2 clock configuration the cpu clock and the memory clock are independent unless the ?synchronous mode? strap option is set (see the strap options chapter). the potential clock configurations are then relatively limited as listed in table 6-4 . the advantage of synchronous mode compared to asynchronous mode is a lower latency when accessing sdram from the cpu or the pci (saves 4 mclk cycles for the first access of the burst). for the same cpu to memory transfer performance, mclk has to be roughly higher by 20mhz in async mode co mpared to sync mode to get the same system performance level (example: 66mhz sync = 86mhz async). prefer the use of sdram with cas latency equals to 3 (cl2) for the best performance. the advantage of asynchronous mode is the capability to reprogram the mclk speed on the fly. this could help for a pplications where power consumption must be optimized. table 6-3 below gives some examples. the right column correspond to the configuration number as described in table 6-4 : obviously, the values for hclk or mclk can be reduced compared to table 6-4 in case there is no need to push the device to its limits, or when avoiding specific frequency ranges (fm radio band for example). 6.3 architecture recommendations this section describes the recommended implementations for the stpc interfaces. for more details, download the reference schematics from the stpc web site. table 6-1. bus mode selection need selection legacy i/o device (floppy, ...), super i/o isa bus dma capability (soundblaster) isa bus flash, sram, basic i/o device local bus fast boot local bus boot flash of 4mb or more local bus programmable chip select local bus table 6-2. main stpc modes cmode hclk mhz cpu clock clock ratio mclk mhz 1 synchronous 100 200 (x2) 100 2 asynchronous 100 200 (x2) 66 3 synchronous 90 180 (x2) 90 4 synchronous 75 188 (x2.5) 75 table 6-3. clock mode selection constraints c need cpu power critical code fits into l1 cache 1 need cpu power code or data does not fit into l1 cache 3 need high pci bandwidth 1 need flexible sdram speed 2 1
stpc? vega 59/86 6.3.1 power decoupling an appropriate decoupling of the various stpc power pins is mandatory for optimum behaviour. when insufficient, the integrity of the signals is deteriorated, the stability of the system is reduced and emc is increased. 6.3.1.1. pll decoupling this is the most important as the stpc clocks are generated from a single 14mhz stage using multiple plls which are highly sensitive analog cells. the frequencies to filter are the 25-50 khz range which correspond to the internal loop bandwidth of the pll and the 10 to 100 mhz frequency of the output. pll power pins can be tied together to simplify the board layout. figure 6-3. pll decoupling 6.3.1.2. decoupling of 3.3v and vcore a power plane for each of these supplies with one decoupling capacitance for each power pin is the minimum. the use of multiple capacitances with values in decade is the best (for example: 10pf, 1nf, 100nf, 10uf), the smaller the value, the closer to the power pin. connecting the various digital power planes th rough capacitances will reduce furthermore the overall impedance and electrical noise. 6.3.2 14mhz oscillator stage the 14.31818 mhz oscillator stage can be implemented using a quartz crystal, which is the preferred and cheaper solution, or using an external 3.3v oscillator. the crystal must be used in its series-cut fundamental mode and not in overtone mode. it must have an equivalent series resistance (esr, sometimes referred to as rm) of less than 50 ohms (typically 8 ohms) and a shunt capacitance (co) of less than 7 pf. the balance capacitors of 16 pf must be added, one connected to each pin, as shown in figure 6-4 . in the event of an external oscillator providing the master clock signal to the stpc device, the lvttl signal should be connected to xtali, as shown in figure 6-4 . as this clock is the reference for all the other on- chip generated clocks, it is strongly recommended to shield this stage , including the 2 wires going to the stpc balls, in order to reduce the jitter to the minimum and reach the optimum system stability. figure 6-4. 14.31818 mhz stage vdd_pll vss_pll pwr 100nf 47uf gnd connections must be as short as possible 15pf 15pf xtalo xtali xtalo xtali 3.3v 1mohm 1
stpc? vega 60/86 6.3.3 sdram the stpc provides all the signals for sdram control. up to 256 mbyte of main memory is supported. all banks must be 64-bit wide. up to four memory banks are available when using 16 mbit devices. up to two banks only can be connected when using 64 mbit, 128 mbit and 256 mbit components, due to the reallocation of the cs2# and cs3# signals. this is described in table 6-4 and table 6-5 . host memory extends to the top of populated sdram. bank 0 must always be populated. figure 6-5 , figure 6-6 and figure 6-7 show some typical implementations. figure 6-5. one memory bank with four chips (16-bit) the purpose of the serial resistors is to reduce signal oscillation and emi by filtering line reflections. the capacitance in has a filtering effect too, while it is used for propagation delay compensation in the two other figures. 1
stpc? vega 61/86 figure 6-6. one memory bank with eight chips (8-bit) figure 6-7. two memory banks with eight chips (8-bit) 1
stpc? vega 62/86 for other implementations like 32-bit sdram devices, refers to the sdram controller signal multiplexing and address mapping described in the following table 6-4 and table 6-5 . 6.3.4 pci bus the pci bus is always active and the following control signals must be pulled-up to 3.3v or 5v through 8k2 resistors even if this bus is not connected to an external device: frame#, trdy#, irdy#, stop#, devsel#, lock#, serr#, pci_req#[2:0]. pci_clko must be connected to pci_clki through a 10 to 33 ohm resistor. figure 6-8 shows a typical implementation. for more information on layout constraints, go to the place and route recommendations section table 6-4. dimm pinout sdram density 16 mbit 64/128 mbit 64/128 mbit 256 mbit stpc i/f internal banks 2 banks 2 banks 4 banks 4 banks dimm pin number ... ma[10:0] ma[10:0] ma[10:0] ma[10:0] ma[10:0] 123 - ma11 ma11 ma11 cs2# (ma11) 126 - ma12 - ma12 cs3# (ma12) 39 - - ba1 (ma12) ba1 cs#3 (ba1) 122 ba0(ma11) ba0 (ma13) ba0 (ma13) ba0 ba0 table 6-5. address mapping address mapping: 16 mbit - two internal banks stpc i/f ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a22 a21 a2 a19 a18 a17 a16 a15 a14 a13 a12 cas address a11 0 a24a23a10a9a8a7a6a5a4a3 address mapping: 64/128 mbit - two internal banks stpc i/f ba0 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 cas address a11 0 0 0 a26a25a10a9a8a7a6a5a4a3 address mapping: 64/128 mbit - four internal banks stpc i/f ba0 ba1 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a12 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 cas address a11 a12 a27 0 a26 a25 a10 a9 a8 a7 a6 a5 a4 a3 address mapping: 256 mbit - four internal banks stpc i/f ba0 ba1 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a12 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 cas address a11 a12 0 0 0 a27 a26 a10 a9 a8 a7 a6 a5 a4 a3 1
stpc? vega 63/86 figure 6-8. typical pci clock routing in the case of higher clock load it is recommended to use a zero-delay clock buffer as described in figure 6-9 . this approach is also recommended when implementing the delay on pciclki according to the pci section of the electrical specifications chapter. figure 6-9. pci clock routing with zero-delay clock buffer pciclki pciclko device a device b device c pll device d cy2305 implementation 1
stpc? vega 64/86 6.3.5 local bus the local bus has all the signals to connect flash devices or i/o devices with the minimum glue logic. figure 6-10 describes how to connect a 16-bit boot flash (the corresponding strap options must be set accordingly). figure 6-10. typical 16-bit boot flash implementation m58lw064d stpc 22 dq[15:0] a[22:1] ce g w rp byte clk le r 3v3 gnd reset# 16 pd[15:0] fcs0# pwr0# sysrsti# prd0# pa[22:1] prd1# pwr1# sts a0 1
stpc? vega 65/86 6.3.6 ipc most of the ipc signals are multiplexed: interrupt inputs, dma request inputs, dma acknowledge outputs. the figure below describes a complete implementation of the irq[15:0] time-multiplexing. when an interrupt line is used internally, the corresponding input can be grounded. in most of the embedded designs, only few interrupts lines are necessary and the glue logic can be simplified. figure 6-11. typical irq multiplexing when the interface is integrated into the stpc, the corresponding interrupt line can be grounded as it is connected internally. for example, if the integrated ide controller is activated, the irq[14] and irq[15] inputs can be grounded. 74x153 1c0 1y 1g irq[0] irq_mux[0] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y irq_mux[1] irq[1] irq[2] irq[3] irq[4] irq[5] irq[6] irq[7] 74x153 1c0 1y 1g irq_mux[2] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y irq_mux[3] irq[8] irq[9] irq[10] irq[11] irq[12] irq[13] irq[14] irq[15] isa_clk2x isa_clk timer 0 keyboard slave pic com2/com4 com1/com3 lpt2 lpt1 rtc mouse fpu pci / ide pci / ide floppy floppy 1
stpc? vega 66/86 the figure below describes a complete implementation of the external glue logic for dma request time-multiplexing and dma acknowledge demultiplexing. like for the interrupt lines, this logic can be simplified when only few dma channels are used in the application. this glue logic is not needed in local bus mode as it does not support dma transfers. figure 6-12. typical dma multiplexing and demultiplexing 74x153 1c0 1y 1g drq[0] dreq_mux[0] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y dreq_mux[1] drq[1] drq[2] drq[3] drq[4] drq[5] drq[6] drq[7] 74x138 y0# a g2b dack0# y1# y2# y3# y4# y5# y6# y7# c b g2a isa_clk2x isa_clk isa, refresh isa, pio isa, fdc isa, pio slave dmac isa isa isa g1 dma_enc[0] dma_enc[1] dma_enc[2] dack1# dack2# dack3# dack5# dack6# dack7# 1
stpc? vega 67/86 6.3.7 ide / isa dynamic demultiplexing some of the isa bus signals are dynamically multiplexed to optimize the pin count. figure 6-13 describes how to implement the external glue logic to demultiplex the ide and isa interfaces. in local bus mode the 74xx245 and nand gates can be removed. figure 6-13. typical ide / isa demultiplexing 6.3.8 basic audio using ide interface when the application requires only basic audio capabilities, an audio dac on the ide interface can avoid using a pci- based audio device (see figure 6-14 ). this low cost solution is not cpu consuming thanks to the dma controller implemented in the ide controller and can generate 16-bit stereo sound. the clock speed is programmable when using the speaker output. figure 6-14. basic audio on ide master# 74xx245 rmrtccs# a b dir oe isaoe# kbcs# rtcrw# rtcds sa[19:8] stpc bus / dd[15:0] la[22] la[23] la[20] la[21] scs1# scs3# pcs1# pcs3# 74xx74 16 q q dd[15:0] d pr rst d[15:0] cs# pcs1 wr# a/b audio out right left stereo dac pdrq sysrsto# speaker pdiow# vcc vcc vcc stpc q q d pr rst note * : the inverter can be removed when the dac cs# is directly connected to gnd * 1
stpc? vega 68/86 6.3.9 usb interface the stpc integrates a usb host interface with a 2-port hub. the only external device needed are the esd protection circuits usbdf01w5 and an usb power supply controller. figure 6-15 describes a typical implementation using these devices. figure 6-15. typical usb implementation poweron stpc tps2014 oc usbdmns[0] usbdpls[0] usbdmns[1] usbdpls[1] 5v connector gnd 9 10 11 12 1 2 6 7 3 4 8 5 100nf 2x 47uf 5 4 6,7,8 5v 2,3 1 usbvcc 100nf 5v tps2014 power decoupling r = 15 ohm r = 15 ohm r = 15 ohm r = 15 ohm usbdf01w5 (note 1) 1 34 5 2 r = 15 ohm r = 15 ohm usbdf01w5 (note 1) 1 34 5 2 note 1: the esd protection will be adequate for most applic ations. in some instances, problems may occur if the devices on the usb chain do not have enough pow er to drive the signals adequately. we therefore recommend that you replace the par t with discrete components and reduc e the value of the capacitor. 100pf 100pf 1
stpc? vega 69/86 6.3.10 jtag interface the stpc integrates a jtag interface for scan- chain and on-board testing. the only external devices needed are the pull up resistors. figure 6- 16 describes a typical implementation using these devices. figure 6-16. typical jtag implementation stpc tclk tdo 3v3 connector 9 10 1 2 6 7 3 4 8 5 tms tdi trst 3v3 3v3 1
stpc? vega 70/86 6.4 place and route recommendations 6.4.1 general recommendations some stpc interfaces run at high speed and need to be carefully routed or even shielded like: 1) memory interface 2) pci bus 3) 14 mhz oscillator stage all clock signals have to be routed first and shielded for speeds of 27mhz or higher. the high speed signals follow the same constraints, as for the memory and pci control signals. the next interfaces to be routed are memory and pci. all the analog noise-sensitive signals have to be routed in a separate area and hence can be routed independently. figure 6-17. shielding signals 6.4.2 pll definition and implementation plls are analog cells which supply the internal stpc clocks. to get the cleanest clock, the jitter on the power supply must be reduced as much as possible. this will result in a more stable system. each of the integrated plls has a dedicated power pin so a single power plane for all of these plls, or one wire for each, or any solution in between which help the layout of the board can be used. powering these pins with one ferrite + capacitances is enough. we recommend at least 2 capacitances: one 'big' (few uf) for power storage, and one or 2 smalls (100nf + 1nf) for noise filtering. ground ring ground pad shielded signal line ground pad shielded signal lines 1
stpc? vega 71/86 6.4.3 memory interface 6.4.3.1. introduction in order to implement sdram memory interfaces which work at clock frequencies of 100 mhz and above, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. the guidelines described below are related to sdram components on dimm modules. for applications where the memories are directly soldered to the motherboard, the pcb should be laid out such that the trace lengths fit within the constraints shown here . the traces could be slightly shorter since the extra routing on the dimm pcb is no longer present but it is then up to the user to verify the timings. 6.4.3.2. sdram clocking scheme the sdram clocking scheme deserves a special mention here. basically the memory clock is generated on-chip through a pll and goes directly to the mclko output pin of the stpc. the nominal frequency is 100 mhz. because of the high load presented to the mclk on the board by the dimms it is recommended to rebuffer the mclko signal on the board and balance the skew to the clock ports of the different dimms and the mclki input pin of stpc. figure 6-18. clock scheme 6.4.3.3. board layout issues the physical layout of the motherboard pcb assumed in this presentation is as shown in figure 6-19 . because all of the memory interface signal balls are located in the same region of the stpc device, it is possible to orientate the device to reduce the trace lengths. the worst case routing length to the dimm1 is estimated to be 100 mm. figure 6-19. dimm placement solid power and ground planes are a must in order to provide good return paths for the signals and to reduce emi and noise. also there should be ample high frequency decoupling between the power and ground planes to provide a low impedance path between the planes for the return paths for signal routings which change la yers. if possible, the traces should be routed adjacent to the same power or ground plane for the length of the trace. for the sdram interface, the most critical signal is the clock. any skew between the clocks at the dimm1 mclki mclko dimm2 pll register pll ma[ ] + control md[63:0] sdram controller 1
stpc? vega 72/86 sdram components and the memory controller will impact the timing budge t. in order to get well matched clocks at all components it is recommended that all the dimm clock pins, stpc memory clock input (mclki) and any other component using the memory clock are individually driven from a low skew clock driver with matched routing lengths. in other words, all clock line lengths that go from the buffer to the memory chips (mclkx) and from the buffer to the stpc (mclki) must be identical. this is shown in figure 6-20 . figure 6-20. clock routing the important factors for the clock buffer are a consistent drive strength and low skew between the outputs. the delay through the buffer is not important so it does not have to be a zero delay pll type buffer. the trace lengths from the clock driver to the dimm ckn pins should be matched exactly. since the propagation speed can vary between pcb layers, the clocks should be routed in a consistent way. the routing to the stpc memory input should be longer by 75 mm to compensate for the extra clock routing on the dimm. also a 20 pf capacitor should be placed as near as possible to the clock input of the stpc to compensate for the dimm?s higher clock load. the impedance of the trace used for the clock routing should be matched to the dimm clock trace impedance (60-75 ohms) . to minimise crosstalk the clocks should be routed with spacing to adjacent tracks of at least twice the clock trace width. for designs which use sdrams directly mounted on the motherboard pcb all the clock trace lengths should be matched exactly. dimm2 dimm1 stpc 35mm 35mm 15mm 10mm 116mm sdram i/f mclko dimm ckn input stpc mclki dimm ckn input dimm ckn input low skew clock driver: l l+75mm* * no additional 75mm when sdram directly soldered on board 1
stpc? vega 73/86 the dimm sockets should be populated starting with the furthest dimm from the stpc device first (dimm1). there are two types of dimm devices; single-row and dual-row. the dual-row devices require two chip select signals to select between the two rows. a stpc device with 4 chip select control lines could control either 4 single-row dimms or 2 dual-row dimms. when only 2 chip select control lines are activated, only two single- row dimms or one dual-row dimm can be controlled. when using dimm modules, schematics have to be done carefully in order to avoid data buses completely crossing on the board. this has to be checked at the library level. in order to achieve the layout shown in figure 6-21 , schematics have to implement the crossing described in figure 6-22 . the dqm signals must be exchanged using the same order. figure 6-21. optimum data bus layout for dimm figure 6-22. schematics for optimum data bus layout for dimm 6.4.3.4. summary for unbuffered dimms the address/control signals will be the most critical fo r timing. the simulations show that for these signals the best way to drive them is to use a para llel termination. for applications where speed is not so critical series termination can be used as this will save power. using a low impedance such as 50 ? for these critical traces is recommended as it both reduces the delay and the overshoot. the other memory interf ace signals will typically be not as critical as the address/control signals. using lower impedance traces is also beneficial for the other signals but if their timing is not as critical as the address/control si gnals they could use the default value. using a lower impedance implies using wider traces which may have an impact on the routing of the board. the layout of this interface can be validated by an electrical simulation using the ibis model available on the stpc web site. dimm stpc sdram i/f d[15:00] d[31:16] d[47:32] d[63:48] md[31:00] md[63:32] md[15:00] md[31:16] md[47:32] md[63:48] d[63:48] d[31:16] d[47:32] d[15:0] dimm stpc 1
stpc? vega 74/86 6.4.4 pci interface 6.4.4.1. introduction in order to achieve a pci interface which works at clock frequencies up to 33mhz, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. 6.4.4.2. pci clocking scheme the pci clocking scheme deserves a special mention here. basically the pci clock (pciclko) is generated on-chip from hclk through a programmable delay line and a clock divider. the nominal frequency is 33mhz. this clock must be looped to pciclki and goes to the internal south bridge through a deskewer. on the contrary, the internal north bridge is clocked by hclk, putting some additionnal constraints on t 0 and t 1 . figure 6-23. clock scheme hclk pll 1/2 1/3 1/4 clock pciclko t 1 pciclki hclk ad[31:0] south north deskewer mux t 0 t 2 delay stpc bridge bridge 1
stpc? vega 75/86 6.4.4.3. board layout issues the physical layout of the motherboard pcb assumed in this presentation is as shown in figure 6-24 . for the pci interface, the most critical signal is the clock. any skew between the clocks at the pci components and the stpc will impact the timing budget. in order to get well matched clocks at all components it is recommended that all the pci clocks are individually driven from a serial resistance with matched routing lengths. in other words, all clock line lengths that go from the resistor to the pci chips (pciclkx) must be identical. the figure below is for pci devices soldered on- board. in the case of a pci slot, the wire length must be shortened by 2.5" to compensate the clock layout on the pci board. the maximum clock skew between all devices is 2ns according to pci specifications. figure 6-24. typical pci clock routing the figure 6-25 describes a typical clock delay implementation. the exact timing constraints are listed in the pci section of the electrical specifications chapter. figure 6-25. clocks relationships length(pciclki) = length(pciclkx) with x = {a,b,c} note : the value of 22 ohms corre sponds to tracks with z 0 = 70 ohms. pciclki pciclko pciclka pciclkb pciclkc device a device b device c pciclko pciclki hclk pciclkx 1
stpc? vega 76/86 6.5 thermal dissipation 6.5.0.1. power saving thermal dissipation of the stpc depends mainly on supply voltage. when the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage to the lower voltage limit, wher e possible. this could save a few 100?s of mw. the second area to look at is unused interfaces and functions. depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. clock speed dynamic adjustment is also a solution that can be used along with the integrated power management unit. 6.5.0.2. thermal balls the standard way to route thermal balls to ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. with such configuration the plastic bga package does 90% of the thermal dissipation through the ground balls, and especially the central thermal balls which are directly connected to the die. the remaining 10% is dissipated through the case. adding a heat sink reduces this value to 85%. as a result, some basic rules must be followed when routing the stpc in order to avoid thermal problems. as the whole ground layer acts as a heat sink, the ground balls must be directly connected to it, as illustrated in figure 6-26 . if one ground layer is not enough, a second ground plane may be added. figure 6-26. ground routing pad for ground ball thru hole to ground layer t o p l a y e r : s i g n a l s p o w e r l a y e r i n t e r n a l l a y e r : s i g n a l s b o t t o m l a y e r : g r o u n d l a y e r note: for better visi bility, ground balls are not all routed. 1
stpc? vega 77/86 when considering thermal dissipation, one of the most important parts of the layout is the connection between the ground balls and the ground layer. a 1-wire connection is shown in figure 6-27 . the use of a 8-mil wire result s in a thermal resistance of 105c/w assuming copper is used (418 w/ m.k). this high value is due to the thickness (34 m) of the copper on the external side of the pcb. figure 6-27. recommended 1-wire power/ground pad layout considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9c/w. this can be easily improved using four 12.5 mil wires to connect to the four vias around the ground pad link as in figure 6-28 . this gives a total of 49 vias and a global resistance for the 36 thermal balls of 0.5c/ w. figure 6-28. recommended 4-wire ground pad layout the use of a ground plane like in figure 6-29 is even better. to avoid solder wicking ov er to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (nsmd pad). this gives a diameter of 33 mil for a 25 mil ground pad. to obtain the optimum ground layout, place the vias directly under the ball pads. in this case no local board distortion is tolerated. solder mask (4 mil) pad for ground ball (diameter = 25 mil) hole to ground layer (diameter = 12 mil) connection wire (width = 12.5 mil) via (diameter = 24 mil) 34 . 5 m il 1 mil = 0.0254 mm 4 via pads for each ground ball 1
stpc? vega 78/86 figure 6-29. optimum layout for central ground ball - top layer 6.5.0.3. heat dissipation the thickness of the co pper on pcb layers is typically 34 m for external layers and 17 m for internal layers. this means that thermal dissipation is not good; high board temperatures are concentrated around the devices and these fall quickly with increased distance. where possible, place a metal layer inside the pcb; this improves dramatically the spread of heat and hence the thermal dissipation of the board. the possibility of using the whole system box for thermal dissipation is very useful in cases of high internal temperatures and low outside temperatures. bottom side of the pbga should be thermally connected to the metal chassis in order to propagate the heat flow through the metal. thermally connecting also the top side will improve furthermore the heat dissipation. figure 6-30 illustrates such an implementation. figure 6-30. use of metal plate for thermal dissipation as the pcb acts as a heat sink, the layout of top and ground layers must be done with care to maximize the board surface dissipating the heat. the only limitation is the risk of losing routing channels. figure 6-31 and figure 6-32 show a partial routing with a good thermal dissipation thanks to an optimized placement of power and signal vias. the ground plane should be on bottom layer for the best heat spreading (thicker layer than internal ones) and dissipation (direct contact with air). via to ground layer pad for ground ball clearance = 6mil diameter = 25 mil hole diameter = 14 mil solder mask diameter = 33 mil external diameter = 37 mil connections = 10 mil metal planes thermal conductor board die 1
stpc? vega 79/86 figure 6-31. layout for good thermal dissipation - top layer 1 a 3.3 v ball 1.8 v ball (core / pll) via stpc ball vss ball (plane / pll) not connected ball 1
stpc? vega 80/86 figure 6-32. recommend signal wiring (top & ground layers) with corresponding heat flow stpc balls external row internal row gnd power power 1
stpc? vega 81/86 6.6 debug methodology in order to bring a stpc-based board to life with the best efficiency, it is recommended to follow the check-list described in this section. 6.6.1 power supplies in parallel with the assembly process, it is useful to get a bare pcb to check the potential short-circuits between the various power and ground planes. this test is also recommended when the first boards are back from assembly. this will avoid unpleasant surprises in ca se of a short-circuit due to a bad soldering. when the system is powered on, all power supplies, including the pll power pins must be checked to be sure the right level is present. see table 4-2. for the exact supported voltage range: vdd_core: 1.8v vdd_xxxpll: 1.8v vdd: 3.3v 6.6.2 boot sequence 6.6.2.1. reset input the checking of the reset sequence is the next step. the waveform of sysrsti# must comply with the timings described in figure 4-3 . this signal must not have glitches and must stay low until the 14.31818mhz output (osc14m) is at the right frequency and the st rap options are stabilized to a valid configuration. in case this clock is no t present, check the 14mhz oscillator stage (see figure 6-3 ). 6.6.2.2. strap options the stpc has been designed to allow configurations for test purposes that differ from the functional configuration. in many cases, the problems at this stage of the debug are the result of bad strap options. this is why it is mandatory to check they are properly setup and sampled during the boot sequence. the list of all the strap options is summarized at the beginning of section 3 6.6.2.3. clocks once osc14m is checked and correct, the next signals to measure are th e host clock (hclk), pci clocks (pci_clko, pci_clki) and memory clock (mclko, mclki). hclk must run at the speed defined by the corresponding strap options (see section 3 ) and must not exceed 133mhz. therefore the appropriate clock multiplication factor must be selected for cpu freque ncies above this limit. pci_clki and pci_clko must be connected as described in figure 6-24 and not be higher than 33mhz. their speed depends on hclk and on the strap option settings in section 3 to ensure a correct behaviour of the device, refer to the timings constraints, refers to section 4.5.4 mclki and mclko must be connected as described in figure 6-5 to figure 6-7 depending on the sdram implementation. the memory clock must run at hclk speed when in synchronous mode and must not be higher than 100mhz in any case. 6.6.2.4. reset output if sysrsti# and all clocks are correct, then the sysrsto# output signal should behave as described in figure 4-3 or figure 4-4 . 6.6.3 isa mode prior to check the isa bus control signals, pci_clki, isa_clk, isa_clk2x, and dev_clk must be running properly. if it is not th e case, it is probably because one of the previous steps has not been completed. 6.6.3.1. first code fetches when booting on the isa bus, the two key signals to check at the very beginning are rmrtccs# and frame#. the first one is a chip select for the boot flash and is multiplexed with the id e interface. it should toggle together with isaoe# and memrd# to fetch the first 16 bytes of code. this corresponds to the loading of the first line of the cpu cache. in case rmrtccs# does not toggle, it is then necessary to check the pci frame# signal. indeed the isa controller is part of the south bridge and all isa bus cycles are visible on the pci bus. if there is no activity on the pci bus, then one of the previous steps has not been checked properly. if there is activity then there must be something conflicting on the isa bus or on the pci bus. 6.6.3.2. boot flash size the isa bus supports 8-bit and 16-bit memory devices. in case of a 16-bit boot flash, the signal 1
stpc? vega 82/86 memcs16# must be activated during rmrtccs# cycle to inform the isa controller of a 16-bit device. 6.6.3.3. post code once the 16 first bytes are fetched and decoded, the cpu core continue its execution depending on the content of these first data. usually, it corresponds to a jump instruction and the code fetching continues, generating read cycles on the isa bus. most of the bios and boot loaders read the content of the flash, decompress it in sdram, and then continue the execution by jumping to the entry point in ram. this boot process ends with a jump to the entry point of the os launcher. these various steps of the booting sequence are coded by the so-called post codes (power-on self-test). a 8-bit code is written to the port 80h at the beginning of each stage of the booting process (i/o write to address 0080h) and can be displayed on two 7-segment display, enabling a fast visual check of the booting completion level. usually, the last post code is 0x00 and corresponds to the jump into the os launcher. when the execution fails or hangs, the last written code stays visible on that display, indicating either the piece of code to analyse, or the area of the hardware that is not working properly. 6.6.4 local bus mode as the local bus controlle r is located in the host interface, there is no a ccess to the cycles on the pci, reducing the amount of signals to check. 6.6.4.1. first code fetches when booting on the local bus, the key signal to check at the very beginning is fcs0# (or fcs0h#). this signal is a chip select for the boot flash and should toggle together with prd# to fetch the first 16 bytes of code. this corresponds to the loading of the first line of the cpu cache. in case fcs0# does not toggle, then one of the previous steps has not been done properly, like hclk speed and cpu clock multiplier (x1, x2). 6.6.4.2. boot flash size the local bus supports 8-bit and 16-bit memory devices. the size of the boot device is defined by the strap option dack_enc[1] as described in section 3 6.6.4.3. post code like in isa mode, post codes can be implemented on the local bus. the difference is that an iocs# must be programmed at i/o address 80h prior to writing these code, the post display being connected to this iocs# and to the lower 8 bits of the bus. 1
stpc? vega 83/86 6.6.5 summary here is a check-list for the stpc board debug from power-on to cpu execution. for each step, in case of failure, verify first the corresponding balls of the stpc: - check if the voltage or activity is correct - search for potential shortcuts. for troubleshooting in steps 5 to 10, verify the related strap options: - value & connection. refer to section 3 - see figure 4-3 or figure 4-4 for timing constraints steps 8a and 9a are for debug in isa mode while steps 8b and 9b are for local bus mode. check: how? troubleshooting 1 power supplies verify that voltage is within specs: - this must include hf & lf noise - avoid full range sweep refer to table 4-4. for values measure voltage near stpc balls: - use very low gnd connection. add a decoupling capacitor: - the smaller the capacitor , the closer to stpc balls. 2 14.318 mhz verify osc14m speed the 2 capacitors used with the quartz must match with the capacitance of the crystal. try other values. 3 sysrsti# (power good) measure sysrsti# of stpc see figure 4-3 for waveforms. verify reset generation circuit: - device reference - component values 5 hclk measure hclk is at selected frequency 25mhz < hclk < 133mhz hclk wire must be as short as possible 6 pci clocks measure pciclko: - maximum is 33mhz by standard - check it is at selected frequency check pciclki equals pciclko verify pciclko loops to pciclki. verify maximum skew between any pci clock branch is below 1,80 ns. in synchronous mode, check mclki. 7 memory clocks measure mclko: - use a low-capacitance probe - maximum is 100mhz - check it is at selected frequency - in sync mode mclk=hclk - in async mode, default is 66mhz check mclki equals mclko verify load on mclki. verify mclk programming (bios setting). 4 sysrsto# measure sysrsto# of stpc see figure 4-3 for waveforms. verify sysrsti# duration. verify sysrsti# has no glitch. verify clocks are running. 8a pci cycles check pci signals are toggling: - frame#, irdy#, trdy#, devsel# - these signals are active low. check, with a logic analyzer, that first pci cycles are the expected ones: memory read starting at address with lower bits to 0xfff0 verify pci slots if the stpc doesn?t boot: - verify data read from boot memory is ok - ensure flash is correctly programmed - ensure cmos is cleared 1
stpc? vega 84/86 9a isa cycles to boot memory check rmrtccs# & memrd# check directly on boot memory pin verify memcs16#: - must not be asserted for 8-bit memory verify iochrdy is not be asserted verify isaoe# pin: - it controls ide / isa bus demultiplexing 8b local bus cycles to boot memory check fcs0# & prd# check directly on boot memory pin verify hclk speed and cpu clock mode. verify 8/16bits strap option. 9b check, with a logic analyzer, that first local bus cycles are the expected one: memory read starting at the top of boot memory less 16 bytes if the stpc doesn?t boot - verify data read from boot memory is ok - ensure flash is correctly programmed - ensure cmos is cleared. 10 the cpu fills its first cache line by fetching 16 bytes from boot memory. then, the first instructions are executed from the cpu. any boot memory access done after the first 16 bytes is due to the instructions executed by the cpu => minimum hardware is correc tly set, cpu executes code. please refer to the bios writer?s guide or program ming manual to go further wi th your board testing. check: how? troubleshooting 1
stpc? vega 85/86 7 ordering information 7.1 ordering information scheme 7.2 order codes 7.3 customer service more information is available on the stmicroelec- tronics internet site http://www.st.com/mcu st pc v1 k e b c stmicroelectronics prefix product family pc: pc compatible product id v1: vega core speed j: 180 mhz k: 200 mhz memory interface speed e: 100 mhz package b: 388 overmoulded bga temperature range c: commercial case temperature (tcase) = 0c to +85c i: industrial case temperature (tcase) = - 40c to +105c (to be validated) part number core frequency (mhz) memory interface speed (mhz) tcase range (c) stpcv1kebc 200 100 0c to +85 stpcv1jebi 180 100 -40c to +105 STPCV1KEBI 200 100 -40c to +105 1
stpc? vega 86/86 8 revision history table 8-1. revision history date revision description of changes 20-oct-04 1 first release on internet information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 1

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